[linux-merge]linux integration; branch, batman-adv/next, updated. batman-adv-for-davem-8944-g185d3da - commits - lists.open-mesh.org

21 Aug 2012

The following commit has been merged in the batman-adv/next branch:
commit 16698918cdb39ae0d9289741ac2a9ed179f8b8ba
Merge: 1f07b62f3205f6ed41759df2892eaf433bc051a1 22c5649eef0fc37532e20c14d2656b28ca708a69
Author: John W. Linville linville@tuxdriver.com
Date:   Wed Aug 15 14:29:37 2012 -0400
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
diff --combined drivers/bcma/host_pci.c
index a6e5672,fc99628..f7b0af7

--- a/drivers/bcma/host_pci.c
+++ b/drivers/bcma/host_pci.c
@@@ -77,8 -77,8 +77,8 @@@ static void bcma_host_pci_write32(struc
  }
#ifdef CONFIG_BCMA_BLOCKIO
- void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
- 			      size_t count, u16 offset, u8 reg_width)
+ static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
+ 				     size_t count, u16 offset, u8 reg_width)
  {
    void __iomem *addr = core->bus->mmio + offset;
    if (core->bus->mapped_core != core)
@@@ -100,8 -100,9 +100,9 @@@
    }
  }
- void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
- 			       size_t count, u16 offset, u8 reg_width)
+ static void bcma_host_pci_block_write(struct bcma_device *core,
+ 				      const void *buffer, size_t count,
+ 				      u16 offset, u8 reg_width)
  {
    void __iomem *addr = core->bus->mmio + offset;
    if (core->bus->mapped_core != core)
@@@ -139,7 -140,7 +140,7 @@@ static void bcma_host_pci_awrite32(stru
    iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
  }
- const struct bcma_host_ops bcma_host_pci_ops = {
+ static const struct bcma_host_ops bcma_host_pci_ops = {
    .read8		= bcma_host_pci_read8,
    .read16		= bcma_host_pci_read16,
    .read32		= bcma_host_pci_read32,
@@@ -272,7 -273,6 +273,7 @@@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci
    { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
    { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
    { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
 +	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
    { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
    { 0, },
  };
diff --combined drivers/net/wireless/b43/main.c
index a140165,5efa778..d97a95b
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@@ -533,11 -533,11 +533,11 @@@ u64 b43_hf_read(struct b43_wldev *dev
  {
    u64 ret;
- 	ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
+ 	ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
    ret <<= 16;
- 	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
+ 	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
    ret <<= 16;
- 	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
+ 	ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
return ret;
  }
@@@ -550,9 -550,9 +550,9 @@@ void b43_hf_write(struct b43_wldev *dev
    lo = (value & 0x00000000FFFFULL);
    mi = (value & 0x0000FFFF0000ULL) >> 16;
    hi = (value & 0xFFFF00000000ULL) >> 32;
- 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
- 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
- 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
+ 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
+ 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
+ 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
  }
/* Read the firmware capabilities bitmask (Opensource firmware only) */
@@@ -2719,37 -2719,32 +2719,37 @@@ static int b43_gpio_init(struct b43_wld
    if (dev->dev->chip_id == 0x4301) {
    	mask |= 0x0060;
    	set |= 0x0060;
 +	} else if (dev->dev->chip_id == 0x5354) {
 +		/* Don't allow overtaking buttons GPIOs */
 +		set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
    }
 -	if (dev->dev->chip_id == 0x5354)
 -		set &= 0xff02;
 +
    if (0 /* FIXME: conditional unknown */ ) {
    	b43_write16(dev, B43_MMIO_GPIO_MASK,
    		    b43_read16(dev, B43_MMIO_GPIO_MASK)
    		    | 0x0100);
 -		mask |= 0x0180;
 -		set |= 0x0180;
 +		/* BT Coexistance Input */
 +		mask |= 0x0080;
 +		set |= 0x0080;
 +		/* BT Coexistance Out */
 +		mask |= 0x0100;
 +		set |= 0x0100;
    }
    if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
 +		/* PA is controlled by gpio 9, let ucode handle it */
    	b43_write16(dev, B43_MMIO_GPIO_MASK,
    		    b43_read16(dev, B43_MMIO_GPIO_MASK)
    		    | 0x0200);
    	mask |= 0x0200;
    	set |= 0x0200;
    }
 -	if (dev->dev->core_rev >= 2)
 -		mask |= 0x0010;	/* FIXME: This is redundant. */
switch (dev->dev->bus_type) {
  #ifdef CONFIG_B43_BCMA
    case B43_BUS_BCMA:
    	bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
    			(bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
 -					BCMA_CC_GPIOCTL) & mask) | set);
 +					BCMA_CC_GPIOCTL) & ~mask) | set);
    	break;
  #endif
  #ifdef CONFIG_B43_SSB
@@@ -2758,7 -2753,7 +2758,7 @@@
    	if (gpiodev)
    		ssb_write32(gpiodev, B43_GPIO_CONTROL,
    			    (ssb_read32(gpiodev, B43_GPIO_CONTROL)
 -				    & mask) | set);
 +				    & ~mask) | set);
    	break;
  #endif
    }
@@@ -4282,6 -4277,35 +4282,35 @@@ out
    return err;
  }
+ static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
+ {
+ 	switch (phy_type) {
+ 	case B43_PHYTYPE_A:
+ 		return "A";
+ 	case B43_PHYTYPE_B:
+ 		return "B";
+ 	case B43_PHYTYPE_G:
+ 		return "G";
+ 	case B43_PHYTYPE_N:
+ 		return "N";
+ 	case B43_PHYTYPE_LP:
+ 		return "LP";
+ 	case B43_PHYTYPE_SSLPN:
+ 		return "SSLPN";
+ 	case B43_PHYTYPE_HT:
+ 		return "HT";
+ 	case B43_PHYTYPE_LCN:
+ 		return "LCN";
+ 	case B43_PHYTYPE_LCNXN:
+ 		return "LCNXN";
+ 	case B43_PHYTYPE_LCN40:
+ 		return "LCN40";
+ 	case B43_PHYTYPE_AC:
+ 		return "AC";
+ 	}
+ 	return "UNKNOWN";
+ }
+ 
  /* Get PHY and RADIO versioning numbers */
  static int b43_phy_versioning(struct b43_wldev *dev)
  {
@@@ -4342,13 -4366,13 +4371,13 @@@
    	unsupported = 1;
    }
    if (unsupported) {
- 		b43err(dev->wl, "FOUND UNSUPPORTED PHY "
- 		       "(Analog %u, Type %u, Revision %u)\n",
- 		       analog_type, phy_type, phy_rev);
+ 		b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
+ 		       analog_type, phy_type, b43_phy_name(dev, phy_type),
+ 		       phy_rev);
    	return -EOPNOTSUPP;
    }
- 	b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
- 	       analog_type, phy_type, phy_rev);
+ 	b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
+ 		analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
/* Get RADIO versioning */
    if (dev->dev->core_rev >= 24) {
diff --combined drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
index 192ad5c,683a865..1c70def
--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
@@@ -86,7 -86,9 +86,9 @@@ MODULE_AUTHOR("Broadcom Corporation")
  MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver.");
  MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
  MODULE_LICENSE("Dual BSD/GPL");
- 
+ /* This needs to be adjusted when brcms_firmwares changes */
+ MODULE_FIRMWARE("brcm/bcm43xx-0.fw");
+ MODULE_FIRMWARE("brcm/bcm43xx_hdr-0.fw");
/* recognized BCMA Core IDs */
  static struct bcma_device_id brcms_coreid_table[] = {
@@@ -121,8 -123,7 +123,8 @@@ static struct ieee80211_channel brcms_2
    	 IEEE80211_CHAN_NO_HT40PLUS),
    CHAN2GHZ(14, 2484,
    	 IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
 -		 IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
 +		 IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
 +		 IEEE80211_CHAN_NO_OFDM)
  };
static struct ieee80211_channel brcms_5ghz_nphy_chantable[] = {
diff --combined include/linux/bcma/bcma_driver_chipcommon.h
index d323a4b,fcb06fb..3fb8bba
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@@ -89,17 -89,12 +89,18 @@@
  #define  BCMA_CC_CHIPST_4313_OTP_PRESENT	2
  #define  BCMA_CC_CHIPST_4331_SPROM_PRESENT	2
  #define  BCMA_CC_CHIPST_4331_OTP_PRESENT	4
 +#define  BCMA_CC_CHIPST_43228_ILP_DIV_EN	0x00000001
 +#define  BCMA_CC_CHIPST_43228_OTP_PRESENT	0x00000002
 +#define  BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL	0x00000004
 +#define  BCMA_CC_CHIPST_43228_SDIO_MODE		0x00000008
 +#define  BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT	0x00000010
 +#define  BCMA_CC_CHIPST_43228_SDIO_RESET	0x00000020
  #define  BCMA_CC_CHIPST_4706_PKG_OPTION		BIT(0) /* 0: full-featured package 1: low-cost package */
  #define  BCMA_CC_CHIPST_4706_SFLASH_PRESENT	BIT(1) /* 0: parallel, 1: serial flash is present */
  #define  BCMA_CC_CHIPST_4706_SFLASH_TYPE	BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
  #define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN	BIT(3) /* 0: little, 1: big endian */
  #define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE	BIT(5) /* PCIE1 enable strap pin */
+ #define  BCMA_CC_CHIPST_5357_NAND_BOOT		BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
  #define BCMA_CC_JCMD			0x0030		/* Rev >= 10 only */
  #define  BCMA_CC_JCMD_START		0x80000000
  #define  BCMA_CC_JCMD_BUSY		0x80000000
@@@ -266,6 -261,29 +267,29 @@@
  #define  BCMA_CC_SROM_CONTROL_SIZE_16K	0x00000004
  #define  BCMA_CC_SROM_CONTROL_SIZE_SHIFT	1
  #define  BCMA_CC_SROM_CONTROL_PRESENT	0x00000001
+ /* Block 0x140 - 0x190 registers are chipset specific */
+ #define BCMA_CC_4706_FLASHSCFG		0x18C		/* Flash struct configuration */
+ #define  BCMA_CC_4706_FLASHSCFG_MASK	0x000000ff
+ #define  BCMA_CC_4706_FLASHSCFG_SF1	0x00000001	/* 2nd serial flash present */
+ #define  BCMA_CC_4706_FLASHSCFG_PF1	0x00000002	/* 2nd parallel flash present */
+ #define  BCMA_CC_4706_FLASHSCFG_SF1_TYPE	0x00000004	/* 2nd serial flash type : 0 : ST, 1 : Atmel */
+ #define  BCMA_CC_4706_FLASHSCFG_NF1	0x00000008	/* 2nd NAND flash present */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK	0x000000f0
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB	0x00000010	/* 4MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB	0x00000020	/* 8MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB	0x00000030	/* 16MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB	0x00000040	/* 32MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB	0x00000050	/* 64MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB	0x00000060	/* 128MB */
+ #define  BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB	0x00000070	/* 256MB */
+ /* NAND flash registers for BCM4706 (corerev = 31) */
+ #define BCMA_CC_NFLASH_CTL		0x01A0
+ #define  BCMA_CC_NFLASH_CTL_ERR		0x08000000
+ #define BCMA_CC_NFLASH_CONF		0x01A4
+ #define BCMA_CC_NFLASH_COL_ADDR		0x01A8
+ #define BCMA_CC_NFLASH_ROW_ADDR		0x01AC
+ #define BCMA_CC_NFLASH_DATA		0x01B0
+ #define BCMA_CC_NFLASH_WAITCNT0		0x01B4
  /* 0x1E0 is defined as shared BCMA_CLKCTLST */
  #define BCMA_CC_HW_WORKAROUND		0x01E4 /* Hardware workaround (rev >= 20) */
  #define BCMA_CC_UART0_DATA		0x0300
@@@ -325,6 -343,60 +349,60 @@@
  #define BCMA_CC_PLLCTL_ADDR		0x0660
  #define BCMA_CC_PLLCTL_DATA		0x0664
  #define BCMA_CC_SPROM			0x0800 /* SPROM beginning */
+ /* NAND flash MLC controller registers (corerev >= 38) */
+ #define BCMA_CC_NAND_REVISION		0x0C00
+ #define BCMA_CC_NAND_CMD_START		0x0C04
+ #define BCMA_CC_NAND_CMD_ADDR_X		0x0C08
+ #define BCMA_CC_NAND_CMD_ADDR		0x0C0C
+ #define BCMA_CC_NAND_CMD_END_ADDR	0x0C10
+ #define BCMA_CC_NAND_CS_NAND_SELECT	0x0C14
+ #define BCMA_CC_NAND_CS_NAND_XOR	0x0C18
+ #define BCMA_CC_NAND_SPARE_RD0		0x0C20
+ #define BCMA_CC_NAND_SPARE_RD4		0x0C24
+ #define BCMA_CC_NAND_SPARE_RD8		0x0C28
+ #define BCMA_CC_NAND_SPARE_RD12		0x0C2C
+ #define BCMA_CC_NAND_SPARE_WR0		0x0C30
+ #define BCMA_CC_NAND_SPARE_WR4		0x0C34
+ #define BCMA_CC_NAND_SPARE_WR8		0x0C38
+ #define BCMA_CC_NAND_SPARE_WR12		0x0C3C
+ #define BCMA_CC_NAND_ACC_CONTROL	0x0C40
+ #define BCMA_CC_NAND_CONFIG		0x0C48
+ #define BCMA_CC_NAND_TIMING_1		0x0C50
+ #define BCMA_CC_NAND_TIMING_2		0x0C54
+ #define BCMA_CC_NAND_SEMAPHORE		0x0C58
+ #define BCMA_CC_NAND_DEVID		0x0C60
+ #define BCMA_CC_NAND_DEVID_X		0x0C64
+ #define BCMA_CC_NAND_BLOCK_LOCK_STATUS	0x0C68
+ #define BCMA_CC_NAND_INTFC_STATUS	0x0C6C
+ #define BCMA_CC_NAND_ECC_CORR_ADDR_X	0x0C70
+ #define BCMA_CC_NAND_ECC_CORR_ADDR	0x0C74
+ #define BCMA_CC_NAND_ECC_UNC_ADDR_X	0x0C78
+ #define BCMA_CC_NAND_ECC_UNC_ADDR	0x0C7C
+ #define BCMA_CC_NAND_READ_ERROR_COUNT	0x0C80
+ #define BCMA_CC_NAND_CORR_STAT_THRESHOLD	0x0C84
+ #define BCMA_CC_NAND_READ_ADDR_X	0x0C90
+ #define BCMA_CC_NAND_READ_ADDR		0x0C94
+ #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X	0x0C98
+ #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR	0x0C9C
+ #define BCMA_CC_NAND_COPY_BACK_ADDR_X	0x0CA0
+ #define BCMA_CC_NAND_COPY_BACK_ADDR	0x0CA4
+ #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X	0x0CA8
+ #define BCMA_CC_NAND_BLOCK_ERASE_ADDR	0x0CAC
+ #define BCMA_CC_NAND_INV_READ_ADDR_X	0x0CB0
+ #define BCMA_CC_NAND_INV_READ_ADDR	0x0CB4
+ #define BCMA_CC_NAND_BLK_WR_PROTECT	0x0CC0
+ #define BCMA_CC_NAND_ACC_CONTROL_CS1	0x0CD0
+ #define BCMA_CC_NAND_CONFIG_CS1		0x0CD4
+ #define BCMA_CC_NAND_TIMING_1_CS1	0x0CD8
+ #define BCMA_CC_NAND_TIMING_2_CS1	0x0CDC
+ #define BCMA_CC_NAND_SPARE_RD16		0x0D30
+ #define BCMA_CC_NAND_SPARE_RD20		0x0D34
+ #define BCMA_CC_NAND_SPARE_RD24		0x0D38
+ #define BCMA_CC_NAND_SPARE_RD28		0x0D3C
+ #define BCMA_CC_NAND_CACHE_ADDR		0x0D40
+ #define BCMA_CC_NAND_CACHE_DATA		0x0D44
+ #define BCMA_CC_NAND_CTRL_CONFIG	0x0D48
+ #define BCMA_CC_NAND_CTRL_STATUS	0x0D4C
/* Divider allocation in 4716/47162/5356 */
  #define BCMA_CC_PMU5_MAINPLL_CPU	1
@@@ -415,6 -487,13 +493,13 @@@
  /* 4313 Chip specific ChipControl register bits */
  #define BCMA_CCTRL_4313_12MA_LED_DRIVE		0x00000007	/* 12 mA drive strengh for later 4313 */
+ /* BCM5357 ChipControl register bits */
+ #define BCMA_CHIPCTL_5357_EXTPA			BIT(14)
+ #define BCMA_CHIPCTL_5357_ANT_MUX_2O3		BIT(15)
+ #define BCMA_CHIPCTL_5357_NFLASH		BIT(16)
+ #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE	BIT(18)
+ #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE	BIT(19)
+ 
  /* Data for the PMU, if available.
   * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
   */
diff --combined net/mac80211/mesh.c
index 8557235,856dcf4..0e2f83e
--- a/net/mac80211/mesh.c
+++ b/net/mac80211/mesh.c
@@@ -136,10 -136,13 +136,13 @@@ bool mesh_peer_accepts_plinks(struct ie
   * mesh_accept_plinks_update - update accepting_plink in local mesh beacons
   *
   * @sdata: mesh interface in which mesh beacons are going to be updated
+  *
+  * Returns: beacon changed flag if the beacon content changed.
   */
- void mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata)
+ u32 mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata)
  {
    bool free_plinks;
+ 	u32 changed = 0;
/* In case mesh_plink_free_count > 0 and mesh_plinktbl_capacity == 0,
     * the mesh interface might be able to establish plinks with peers that
@@@ -149,8 -152,12 +152,12 @@@
     */
    free_plinks = mesh_plink_availables(sdata);
- 	if (free_plinks != sdata->u.mesh.accepting_plinks)
- 		ieee80211_mesh_housekeeping_timer((unsigned long) sdata);
+ 	if (free_plinks != sdata->u.mesh.accepting_plinks) {
+ 		sdata->u.mesh.accepting_plinks = free_plinks;
+ 		changed = BSS_CHANGED_BEACON;
+ 	}
+ 
+ 	return changed;
  }
int mesh_rmc_init(struct ieee80211_sub_if_data *sdata)
@@@ -262,7 -269,6 +269,6 @@@ mesh_add_meshconf_ie(struct sk_buff *sk
    neighbors = (neighbors > 15) ? 15 : neighbors;
    *pos++ = neighbors << 1;
    /* Mesh capability */
- 	ifmsh->accepting_plinks = mesh_plink_availables(sdata);
    *pos = MESHCONF_CAPAB_FORWARDING;
    *pos |= ifmsh->accepting_plinks ?
        MESHCONF_CAPAB_ACCEPT_PLINKS : 0x00;
@@@ -521,14 -527,13 +527,13 @@@ int ieee80211_new_mesh_header(struct ie
  static void ieee80211_mesh_housekeeping(struct ieee80211_sub_if_data *sdata,
    		   struct ieee80211_if_mesh *ifmsh)
  {
- 	bool free_plinks;
+ 	u32 changed;
ieee80211_sta_expire(sdata, IEEE80211_MESH_PEER_INACTIVITY_LIMIT);
    mesh_path_expire(sdata);
- 	free_plinks = mesh_plink_availables(sdata);
- 	if (free_plinks != sdata->u.mesh.accepting_plinks)
- 		ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON);
+ 	changed = mesh_accept_plinks_update(sdata);
+ 	ieee80211_bss_info_change_notify(sdata, changed);
mod_timer(&ifmsh->housekeeping_timer,
    	  round_jiffies(jiffies + IEEE80211_MESH_HOUSEKEEPING_INTERVAL));
@@@ -622,7 -627,6 +627,7 @@@ void ieee80211_stop_mesh(struct ieee802
del_timer_sync(&sdata->u.mesh.housekeeping_timer);
    del_timer_sync(&sdata->u.mesh.mesh_path_root_timer);
 +	del_timer_sync(&sdata->u.mesh.mesh_path_timer);
    /*
     * If the timer fired while we waited for it, it will have
     * requeued the work. Now the work will be running again
@@@ -635,8 -639,6 +640,8 @@@
    local->fif_other_bss--;
    atomic_dec(&local->iff_allmultis);
    ieee80211_configure_filter(local);
 +
 +	sdata->u.mesh.timers_running = 0;
  }
static void ieee80211_mesh_rx_bcn_presp(struct ieee80211_sub_if_data *sdata,
-- 
linux integration

    