The following commit has been merged in the linux branch: commit 74eee2e8d08048c847d1998c686e12a477ff939a Author: Bruce Allan bruce.w.allan@intel.com Date: Thu Oct 22 21:22:18 2009 -0700

e1000e: reset the PHY on 82577/82578 when going to Sx

The PHY on 82577/82578 parts needs a soft reset when transitioning to Sx state in order for the PHY write which disables gigabit speed to take effect. Gigabit speed must be disabled in order for the PHY writes to registers on page 800 (the wakeup control registers) to work as expected otherwise the system might not wake via WoL.

Signed-off-by: Bruce Allan bruce.w.allan@intel.com Signed-off-by: Jeff Kirsher jeffrey.t.kirsher@intel.com Signed-off-by: David S. Miller davem@davemloft.net

diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 99df2ab..aa0ab0e 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -2843,9 +2843,8 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) E1000_PHY_CTRL_GBE_DISABLE; ew32(PHY_CTRL, phy_ctrl);

- /* Workaround SWFLAG unexpectedly set during S0->Sx */ if (hw->mac.type == e1000_pchlan) - udelay(500); + e1000_phy_hw_reset_ich8lan(hw); default: break; }