[linux-next] LinuxNextTracking branch, master, updated. next-20220328

28 Mar 2022

The following commit has been merged in the master branch:
commit b14ffae378aa1db993e62b01392e70d1e585fb23
Merge: 52deda9551a01879b3562e7b41748e85c591f14c c6e90a1c660874736bd09c1fec6312b4b4c2ff7b
Author: Linus Torvalds torvalds@linux-foundation.org
Date:   Thu Mar 24 16:19:43 2022 -0700
Merge tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
     "Lots of work all over, Intel improving DG2 support, amdkfd CRIU
      support, msm new hw support, and faster fbdev support.
dma-buf:
       - rename dma-buf-map to iosys-map
core:
       - move buddy allocator to core
       - add pci/platform init macros
       - improve EDID parser deep color handling
       - EDID timing type 7 support
       - add GPD Win Max quirk
       - add yes/no helpers to string_helpers
       - flatten syncobj chains
       - add nomodeset support to lots of drivers
       - improve fb-helper clipping support
       - add default property value interface
fbdev:
       - improve fbdev ops speed
ttm:
       - add a backpointer from ttm bo->ttm resource
dp:
       - move displayport headers
       - add a dp helper module
bridge:
       - anx7625 atomic support, HDCP support
panel:
       - split out panel-lvds and lvds bindings
       - find panels in OF subnodes
privacy:
       - add chromeos privacy screen support
fb:
       - hot unplug fw fb on forced removal
simpledrm:
       - request region instead of marking ioresource busy
       - add panel oreintation property
udmabuf:
       - fix oops with 0 pages
amdgpu:
       - power management code cleanup
       - Enable freesync video mode by default
       - RAS code cleanup
       - Improve VRAM access for debug using SDMA
       - SR-IOV rework special register access and fixes
       - profiling power state request ioctl
       - expose IP discovery via sysfs
       - Cyan skillfish updates
       - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates
       - expose benchmark tests via debugfs
       - add module param to disable XGMI for testing
       - GPU reset debugfs register dumping support
amdkfd:
       - CRIU support
       - SDMA queue fixes
radeon:
       - UVD suspend fix
       - iMac backlight fix
i915:
       - minimal parallel submission for execlists
       - DG2-G12 subplatform added
       - DG2 programming workarounds
       - DG2 accelerated migration support
       - flat CCS and CCS engine support for XeHP
       - initial small BAR support
       - drop fake LMEM support
       - ADL-N PCH support
       - bigjoiner updates
       - introduce VMA resources and async unbinding
       - register definitions cleanups
       - multi-FBC refactoring
       - DG1 OPROM over SPI support
       - ADL-N platform enabling
       - opregion mailbox #5 support
       - DP MST ESI improvements
       - drm device based logging
       - async flip optimisation for DG2
       - CPU arch abstraction fixes
       - improve GuC ADS init to work on aarch64
       - tweak TTM LRU priority hint
       - GuC 69.0.3 support
       - remove short term execbuf pins
nouveau:
       - higher DP/eDP bitrates
       - backlight fixes
msm:
       - dpu + dp support for sc8180x
       - dp support for sm8350
       - dpu + dsi support for qcm2290
       - 10nm dsi phy tuning support
       - bridge support for dp encoder
       - gpu support for additional 7c3 SKUs
ingenic:
       - HDMI support for JZ4780
       - aux channel EDID support
ast:
       - AST2600 support
       - add wide screen support
       - create DP/DVI connectors
omapdrm:
       - fix implicit dma_buf fencing
vc4:
       - add CSC + full range support
       - better display firmware handoff
panfrost:
       - add initial dual-core GPU support
stm:
       - new revision support
       - fb handover support
mediatek:
       - transfer display binding document to yaml format.
       - add mt8195 display device binding.
       - allow commands to be sent during video mode.
       - add wait_for_event for crtc disable by cmdq.
tegra:
       - YUV format support
rcar-du:
       - LVDS support for M3-W+ (R8A77961)
exynos:
       - BGR pixel format for FIMD device"
* tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm: (1529 commits)
      drm/i915/display: Do not re-enable PSR after it was marked as not reliable
      drm/i915/display: Fix HPD short pulse handling for eDP
      drm/amdgpu: Use drm_mode_copy()
      drm/radeon: Use drm_mode_copy()
      drm/amdgpu: Use ternary operator in `vcn_v1_0_start()`
      drm/amdgpu: Remove pointless on stack mode copies
      drm/amd/pm: fix indenting in __smu_cmn_reg_print_error()
      drm/amdgpu/dc: fix typos in comments
      drm/amdgpu: fix typos in comments
      drm/amd/pm: fix typos in comments
      drm/amdgpu: Add stolen reserved memory for MI25 SRIOV.
      drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations.
      drm/amdkfd: evict svm bo worker handle error
      drm/amdgpu/vcn: fix vcn ring test failure in igt reload test
      drm/amdgpu: only allow secure submission on rings which support that
      drm/amdgpu: fixed the warnings reported by kernel test robot
      drm/amd/display: 3.2.177
      drm/amd/display: [FW Promotion] Release 0.0.108.0
      drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2
      drm/amd/display: Wait for hubp read line for Pollock
      ...
diff --combined Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
index 25b5ef3f759c,0d38d6fe3983..35a48515836e

--- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
@@@ -83,6 -83,9 +83,9 @@@ properties
      type: boolean
      description: let the driver enable audio HDMI codec function or not.
+   aux-bus:
+     $ref: /schemas/display/dp-aux-bus.yaml#
+ 
    ports:
      $ref: /schemas/graph.yaml#/properties/ports
@@@ -91,7 -94,22 +94,7 @@@
          $ref: /schemas/graph.yaml#/$defs/port-base
          unevaluatedProperties: false
          description:
 -          MIPI DSI/DPI input.
 -
 -        properties:
 -          endpoint:
 -            $ref: /schemas/media/video-interfaces.yaml#
 -            type: object
 -            additionalProperties: false
 -
 -            properties:
 -              remote-endpoint: true
 -
 -              bus-type:
 -                enum: [1, 5]
 -                default: 1
 -
 -              data-lanes: true
 +          Video port for MIPI DSI input.
port@1:
          $ref: /schemas/graph.yaml#/properties/port
@@@ -140,6 -158,8 +143,6 @@@ examples
                      reg = <0>;
                      anx7625_in: endpoint {
                          remote-endpoint = <&mipi_dsi>;
 -                        bus-type = <5>;
 -                        data-lanes = <0 1 2 3>;
                      };
                  };
@@@ -150,5 -170,19 +153,19 @@@
                      };
                  };
              };
+ 
+             aux-bus {
+                 panel {
+                     compatible = "innolux,n125hce-gn1";
+                     power-supply = <&pp3300_disp_x>;
+                     backlight = <&backlight_lcd0>;
+ 
+                     port {
+                         panel_in: endpoint {
+                             remote-endpoint = <&anx7625_out>;
+                         };
+                     };
+                 };
+             };
          };
      };
diff --combined Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
index 000000000000,611a2dbdefa4..e3cef99d0f98
mode 000000,100644..100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@@ -1,0 -1,88 +1,78 @@@
+ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ %YAML 1.2
+ ---
+ $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
+ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Mediatek display overlay 2 layer
+ 
+ maintainers:
+   - Chun-Kuang Hu chunkuang.hu@kernel.org
+   - Philipp Zabel p.zabel@pengutronix.de
+ 
+ description: |
+   Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
+   for OVL.
+   OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
+   For a description of the MMSYS_CONFIG binding, see
+   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+   for details.
+ 
+ properties:
+   compatible:
+     oneOf:
+       - items:
+           - const: mediatek,mt8183-disp-ovl-2l
+       - items:
+           - const: mediatek,mt8192-disp-ovl-2l
+ 
+   reg:
+     maxItems: 1
+ 
+   interrupts:
+     maxItems: 1
+ 
+   power-domains:
+     description: A phandle and PM domain specifier as defined by bindings of
+       the power controller specified by phandle. See
+       Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ 
+   clocks:
+     items:
+       - description: OVL-2L Clock
+ 
+   iommus:
+     description:
+       This property should point to the respective IOMMU block with master port as argument,
+       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ 
 -  mediatek,larb:
 -    description:
 -      This property should contain a phandle pointing to the local arbiter devices defined in
 -      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
 -      It must sort according to the local arbiter index, like larb0, larb1, larb2...
 -    $ref: /schemas/types.yaml#/definitions/phandle-array
 -    minItems: 1
 -    maxItems: 32
 -
+   mediatek,gce-client-reg:
+     description: The register of client driver can be configured by gce with
+       4 arguments defined in this property, such as phandle of gce, subsys id,
+       register offset and size. Each GCE subsys id is mapping to a client
+       defined in the header include/dt-bindings/gce/<chip>-gce.h.
+     $ref: /schemas/types.yaml#/definitions/phandle-array
+     maxItems: 1
+ 
+ required:
+   - compatible
+   - reg
+   - interrupts
+   - power-domains
+   - clocks
+   - iommus
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+ 
+     ovl_2l0: ovl@14009000 {
+         compatible = "mediatek,mt8183-disp-ovl-2l";
+         reg = <0 0x14009000 0 0x1000>;
+         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+         clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+         iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
 -        mediatek,larb = <&larb0>;
+         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+     };
diff --combined Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 000000000000,e71f79bc2dee..93d5c68a2dbd
mode 000000,100644..100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@@ -1,0 -1,103 +1,93 @@@
+ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ %YAML 1.2
+ ---
+ $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
+ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Mediatek display overlay
+ 
+ maintainers:
+   - Chun-Kuang Hu chunkuang.hu@kernel.org
+   - Philipp Zabel p.zabel@pengutronix.de
+ 
+ description: |
+   Mediatek display overlay, namely OVL, can do alpha blending from
+   the memory.
+   OVL device node must be siblings to the central MMSYS_CONFIG node.
+   For a description of the MMSYS_CONFIG binding, see
+   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+   for details.
+ 
+ properties:
+   compatible:
+     oneOf:
+       - items:
+           - const: mediatek,mt2701-disp-ovl
+       - items:
+           - const: mediatek,mt8173-disp-ovl
+       - items:
+           - const: mediatek,mt8183-disp-ovl
+       - items:
+           - const: mediatek,mt8192-disp-ovl
+       - items:
+           - enum:
+               - mediatek,mt7623-disp-ovl
+               - mediatek,mt2712-disp-ovl
+           - enum:
+               - mediatek,mt2701-disp-ovl
+       - items:
+           - enum:
+               - mediatek,mt8195-disp-ovl
+           - enum:
+               - mediatek,mt8183-disp-ovl
+ 
+   reg:
+     maxItems: 1
+ 
+   interrupts:
+     maxItems: 1
+ 
+   power-domains:
+     description: A phandle and PM domain specifier as defined by bindings of
+       the power controller specified by phandle. See
+       Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ 
+   clocks:
+     items:
+       - description: OVL Clock
+ 
+   iommus:
+     description:
+       This property should point to the respective IOMMU block with master port as argument,
+       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ 
 -  mediatek,larb:
 -    description:
 -      This property should contain a phandle pointing to the local arbiter devices defined in
 -      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
 -      It must sort according to the local arbiter index, like larb0, larb1, larb2...
 -    $ref: /schemas/types.yaml#/definitions/phandle-array
 -    minItems: 1
 -    maxItems: 32
 -
+   mediatek,gce-client-reg:
+     description: The register of client driver can be configured by gce with
+       4 arguments defined in this property, such as phandle of gce, subsys id,
+       register offset and size. Each GCE subsys id is mapping to a client
+       defined in the header include/dt-bindings/gce/<chip>-gce.h.
+     $ref: /schemas/types.yaml#/definitions/phandle-array
+     maxItems: 1
+ 
+ required:
+   - compatible
+   - reg
+   - interrupts
+   - power-domains
+   - clocks
+   - iommu
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+ 
+     ovl0: ovl@1400c000 {
+         compatible = "mediatek,mt8173-disp-ovl";
+         reg = <0 0x1400c000 0 0x1000>;
+         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+         clocks = <&mmsys CLK_MM_DISP_OVL0>;
+         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 -        mediatek,larb = <&larb0>;
+         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+     };
diff --combined Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 000000000000,8ef821641672..b56e22fbcd52
mode 000000,100644..100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@@ -1,0 -1,117 +1,107 @@@
+ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ %YAML 1.2
+ ---
+ $id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
+ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Mediatek Read Direct Memory Access
+ 
+ maintainers:
+   - Chun-Kuang Hu chunkuang.hu@kernel.org
+   - Philipp Zabel p.zabel@pengutronix.de
+ 
+ description: |
+   Mediatek Read Direct Memory Access(RDMA) component used to read the
+   data into DMA. It provides real time data to the back-end panel
+   driver, such as DSI, DPI and DP_INTF.
+   It contains one line buffer to store the sufficient pixel data.
+   RDMA device node must be siblings to the central MMSYS_CONFIG node.
+   For a description of the MMSYS_CONFIG binding, see
+   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+   for details.
+ 
+ properties:
+   compatible:
+     oneOf:
+       - items:
+           - const: mediatek,mt2701-disp-rdma
+       - items:
+           - const: mediatek,mt8173-disp-rdma
+       - items:
+           - const: mediatek,mt8183-disp-rdma
+       - items:
+           - const: mediatek,mt8195-disp-rdma
+       - items:
+           - enum:
+               - mediatek,mt7623-disp-rdma
+               - mediatek,mt2712-disp-rdma
+           - enum:
+               - mediatek,mt2701-disp-rdma
+       - items:
+           - enum:
+               - mediatek,mt8192-disp-rdma
+           - enum:
+               - mediatek,mt8183-disp-rdma
+ 
+   reg:
+     maxItems: 1
+ 
+   interrupts:
+     maxItems: 1
+ 
+   power-domains:
+     description: A phandle and PM domain specifier as defined by bindings of
+       the power controller specified by phandle. See
+       Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ 
+   clocks:
+     items:
+       - description: RDMA Clock
+ 
+   iommus:
+     description:
+       This property should point to the respective IOMMU block with master port as argument,
+       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ 
 -  mediatek,larb:
 -    description:
 -      This property should contain a phandle pointing to the local arbiter devices defined in
 -      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
 -      It must sort according to the local arbiter index, like larb0, larb1, larb2...
 -    $ref: /schemas/types.yaml#/definitions/phandle-array
 -    minItems: 1
 -    maxItems: 32
 -
+   mediatek,rdma-fifo-size:
+     description:
+       rdma fifo size may be different even in same SOC, add this property to the
+       corresponding rdma.
+       The value below is the Max value which defined in hardware data sheet
+       mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+       mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+       mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+     $ref: /schemas/types.yaml#/definitions/uint32
+     enum: [8192, 5120, 2048]
+ 
+   mediatek,gce-client-reg:
+     description: The register of client driver can be configured by gce with
+       4 arguments defined in this property, such as phandle of gce, subsys id,
+       register offset and size. Each GCE subsys id is mapping to a client
+       defined in the header include/dt-bindings/gce/<chip>-gce.h.
+     $ref: /schemas/types.yaml#/definitions/phandle-array
+     maxItems: 1
+ 
+ required:
+   - compatible
+   - reg
+   - interrupts
+   - power-domains
+   - clocks
+   - iommus
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+ 
+     rdma0: rdma@1400e000 {
+         compatible = "mediatek,mt8173-disp-rdma";
+         reg = <0 0x1400e000 0 0x1000>;
+         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 -        mediatek,larb = <&larb0>;
+         mediatek,rdma-fifosize = <8192>;
+         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+     };
diff --combined Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index 000000000000,aaf5649b6413..f9f00a518edf
mode 000000,100644..100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@@ -1,0 -1,86 +1,76 @@@
+ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ %YAML 1.2
+ ---
+ $id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
+ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Mediatek Write Direct Memory Access
+ 
+ maintainers:
+   - Chun-Kuang Hu chunkuang.hu@kernel.org
+   - Philipp Zabel p.zabel@pengutronix.de
+ 
+ description: |
+   Mediatek Write Direct Memory Access(WDMA) component used to write
+   the data into DMA.
+   WDMA device node must be siblings to the central MMSYS_CONFIG node.
+   For a description of the MMSYS_CONFIG binding, see
+   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+   for details.
+ 
+ properties:
+   compatible:
+     oneOf:
+       - items:
+           - const: mediatek,mt8173-disp-wdma
+ 
+   reg:
+     maxItems: 1
+ 
+   interrupts:
+     maxItems: 1
+ 
+   power-domains:
+     description: A phandle and PM domain specifier as defined by bindings of
+       the power controller specified by phandle. See
+       Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ 
+   clocks:
+     items:
+       - description: WDMA Clock
+ 
+   iommus:
+     description:
+       This property should point to the respective IOMMU block with master port as argument,
+       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ 
 -  mediatek,larb:
 -    description:
 -      This property should contain a phandle pointing to the local arbiter devices defined in
 -      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
 -      It must sort according to the local arbiter index, like larb0, larb1, larb2...
 -    $ref: /schemas/types.yaml#/definitions/phandle-array
 -    minItems: 1
 -    maxItems: 32
 -
+   mediatek,gce-client-reg:
+     description: The register of client driver can be configured by gce with
+       4 arguments defined in this property, such as phandle of gce, subsys id,
+       register offset and size. Each GCE subsys id is mapping to a client
+       defined in the header include/dt-bindings/gce/<chip>-gce.h.
+     $ref: /schemas/types.yaml#/definitions/phandle-array
+     maxItems: 1
+ 
+ required:
+   - compatible
+   - reg
+   - interrupts
+   - power-domains
+   - clocks
+   - iommus
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+ 
+     wdma0: wdma@14011000 {
+         compatible = "mediatek,mt8173-disp-wdma";
+         reg = <0 0x14011000 0 0x1000>;
+         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
 -        mediatek,larb = <&larb0>;
+         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+     };
diff --combined MAINTAINERS
index 91c04cb65247,18d799bb66ec..e1c83998b858
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@@ -389,11 -389,11 +389,11 @@@ L:	linux-arm-kernel@lists.infradead.or
  S:	Maintained
  F:	drivers/acpi/arm64
-ACPI I2C MULTI INSTANTIATE DRIVER
 +ACPI SERIAL MULTI INSTANTIATE DRIVER
  M:	Hans de Goede hdegoede@redhat.com
  L:	platform-driver-x86@vger.kernel.org
  S:	Maintained
 -F:	drivers/platform/x86/i2c-multi-instantiate.c
 +F:	drivers/platform/x86/serial-multi-instantiate.c
ACPI PCC(Platform Communication Channel) MAILBOX DRIVER
  M:	Sudeep Holla sudeep.holla@arm.com
@@@ -1002,7 -1002,6 +1002,7 @@@ L:	linux-pm@vger.kernel.or
  S:	Supported
  F:	Documentation/admin-guide/pm/amd-pstate.rst
  F:	drivers/cpufreq/amd-pstate*
 +F:	tools/power/x86/amd_pstate_tracer/amd_pstate_trace.py
AMD PTDMA DRIVER
  M:	Sanjay R Mehta sanju.mehta@amd.com
@@@ -1032,15 -1031,6 +1032,15 @@@ S:	Maintaine
  F:	Documentation/hid/amd-sfh*
  F:	drivers/hid/amd-sfh-hid/
+AMPHION VPU CODEC V4L2 DRIVER
 +M:	Ming Qian ming.qian@nxp.com
 +M:	Shijie Qin shijie.qin@nxp.com
 +M:	Zhou Peng eagle.zhou@nxp.com
 +L:	linux-media@vger.kernel.org
 +S:	Maintained
 +F:	Documentation/devicetree/bindings/media/amphion,vpu.yaml
 +F:	drivers/media/platform/amphion/
 +
  AMS AS73211 DRIVER
  M:	Christian Eggers ceggers@arri.de
  L:	linux-iio@vger.kernel.org
@@@ -1239,6 -1229,18 +1239,6 @@@ S:	Supporte
  F:	drivers/clk/analogbits/*
  F:	include/linux/clk/analogbits*
-ANDES ARCHITECTURE
 -M:	Nick Hu nickhu@andestech.com
 -M:	Greentime Hu green.hu@gmail.com
 -M:	Vincent Chen deanbo422@gmail.com
 -S:	Supported
 -T:	git https://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux.git
 -F:	Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
 -F:	Documentation/devicetree/bindings/nds32/
 -F:	arch/nds32/
 -N:	nds32
 -K:	nds32
 -
  ANDROID CONFIG FRAGMENTS
  M:	Rob Herring robh@kernel.org
  S:	Supported
@@@ -1685,9 -1687,9 +1685,9 @@@ S:	Maintaine
  F:	drivers/clk/sunxi/
ARM/Allwinner sunXi SoC support
 -M:	Maxime Ripard mripard@kernel.org
  M:	Chen-Yu Tsai wens@csie.org
 -R:	Jernej Skrabec jernej.skrabec@gmail.com
 +M:	Jernej Skrabec jernej.skrabec@gmail.com
 +M:	Samuel Holland samuel@sholland.org
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:	Maintained
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
@@@ -1767,7 -1769,7 +1767,7 @@@ T:	git https://github.com/AsahiLinux/li
  F:	Documentation/devicetree/bindings/arm/apple.yaml
  F:	Documentation/devicetree/bindings/arm/apple/*
  F:	Documentation/devicetree/bindings/i2c/apple,i2c.yaml
 -F:	Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
 +F:	Documentation/devicetree/bindings/interrupt-controller/apple,*
  F:	Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
  F:	Documentation/devicetree/bindings/pci/apple,pcie.yaml
  F:	Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
@@@ -2117,6 -2119,13 +2117,6 @@@ F:	Documentation/devicetree/bindings/ar
  F:	arch/arm64/boot/dts/intel/keembay-evm.dts
  F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
-ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
 -M:	Jonathan Cameron jic23@cam.ac.uk
 -L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 -S:	Maintained
 -F:	arch/arm/mach-pxa/stargate2.c
 -F:	drivers/pcmcia/pxa2xx_stargate2.c
 -
  ARM/INTEL XSC3 (MANZANO) ARM CORE
  M:	Lennert Buytenhek kernel@wantstofly.org
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -2245,7 -2254,7 +2245,7 @@@ F:	drivers/phy/mediatek
  ARM/Microchip (AT91) SoC support
  M:	Nicolas Ferre nicolas.ferre@microchip.com
  M:	Alexandre Belloni alexandre.belloni@bootlin.com
 -M:	Ludovic Desroches ludovic.desroches@microchip.com
 +M:	Claudiu Beznea claudiu.beznea@microchip.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:	Supported
  W:	http://www.linux4sam.org
@@@ -2358,7 -2367,6 +2358,7 @@@ L:	openbmc@lists.ozlabs.org (moderated 
  S:	Supported
  F:	Documentation/devicetree/bindings/*/*/*npcm*
  F:	Documentation/devicetree/bindings/*/*npcm*
 +F:	Documentation/devicetree/bindings/arm/npcm/*
  F:	arch/arm/boot/dts/nuvoton-npcm*
  F:	arch/arm/mach-npcm/
  F:	drivers/*/*npcm*
@@@ -2369,7 -2377,6 +2369,7 @@@ ARM/NUVOTON WPCM450 ARCHITECTUR
  M:	Jonathan Neusch��fer j.neuschaefer@gmx.net
  L:	openbmc@lists.ozlabs.org (moderated for non-subscribers)
  S:	Maintained
 +W:	https://github.com/neuschaefer/wpcm450/wiki
  F:	Documentation/devicetree/bindings/*/*wpcm*
  F:	arch/arm/boot/dts/nuvoton-wpcm450*
  F:	arch/arm/mach-npcm/wpcm450.c
@@@ -2524,7 -2531,6 +2524,7 @@@ M:	Magnus Damm <magnus.damm@gmail.com
  L:	linux-renesas-soc@vger.kernel.org
  S:	Supported
  Q:	http://patchwork.kernel.org/project/linux-renesas-soc/list/
 +C:	irc://irc.libera.chat/renesas-soc
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
  F:	Documentation/devicetree/bindings/arm/renesas.yaml
  F:	arch/arm64/boot/dts/renesas/
@@@ -2566,7 -2572,7 +2566,7 @@@ F:	sound/soc/rockchip
  N:	rockchip
ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  R:	Alim Akhtar alim.akhtar@samsung.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  L:	linux-samsung-soc@vger.kernel.org
@@@ -2608,7 -2614,7 +2608,7 @@@ M:	��ukasz Stelmach <l.stelmach@samsung
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  L:	linux-media@vger.kernel.org
  S:	Maintained
 -F:	drivers/media/platform/s5p-g2d/
 +F:	drivers/media/platform/samsung/s5p-g2d/
ARM/SAMSUNG S5P SERIES HDMI CEC SUBSYSTEM SUPPORT
  M:	Marek Szyprowski m.szyprowski@samsung.com
@@@ -2625,7 -2631,7 +2625,7 @@@ M:	Sylwester Nawrocki <s.nawrocki@samsu
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  L:	linux-media@vger.kernel.org
  S:	Maintained
 -F:	drivers/media/platform/s5p-jpeg/
 +F:	drivers/media/platform/samsung/s5p-jpeg/
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
  M:	Marek Szyprowski m.szyprowski@samsung.com
@@@ -2633,7 -2639,7 +2633,7 @@@ M:	Andrzej Hajda <andrzej.hajda@intel.c
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  L:	linux-media@vger.kernel.org
  S:	Maintained
 -F:	drivers/media/platform/s5p-mfc/
 +F:	drivers/media/platform/samsung/s5p-mfc/
ARM/SHMOBILE ARM ARCHITECTURE
  M:	Geert Uytterhoeven geert+renesas@glider.be
@@@ -2641,7 -2647,6 +2641,7 @@@ M:	Magnus Damm <magnus.damm@gmail.com
  L:	linux-renesas-soc@vger.kernel.org
  S:	Supported
  Q:	http://patchwork.kernel.org/project/linux-renesas-soc/list/
 +C:	irc://irc.libera.chat/renesas-soc
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
  F:	Documentation/devicetree/bindings/arm/renesas.yaml
  F:	arch/arm/boot/dts/emev2*
@@@ -2703,7 -2708,7 +2703,7 @@@ F:	drivers/clocksource/clksrc_st_lpc.
  F:	drivers/cpufreq/sti-cpufreq.c
  F:	drivers/dma/st_fdma*
  F:	drivers/i2c/busses/i2c-st.c
 -F:	drivers/media/platform/sti/c8sectpfe/
 +F:	drivers/media/platform/st/sti/c8sectpfe/
  F:	drivers/media/rc/st_rc.c
  F:	drivers/mmc/host/sdhci-st.c
  F:	drivers/phy/st/phy-miphy28lp.c
@@@ -2734,7 -2739,7 +2734,7 @@@ N:	stm3
  N:	stm
ARM/Synaptics SoC support
 -M:	Jisheng Zhang Jisheng.Zhang@synaptics.com
 +M:	Jisheng Zhang jszhang@kernel.org
  M:	Sebastian Hesselbarth sebastian.hesselbarth@gmail.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:	Maintained
@@@ -2755,14 -2760,6 +2755,14 @@@ S:	Maintaine
  F:	Documentation/devicetree/bindings/media/tegra-cec.txt
  F:	drivers/media/cec/platform/tegra/
+ARM/TESLA FSD SoC SUPPORT
 +M:	Alim Akhtar alim.akhtar@samsung.com
 +M:	linux-fsd@tesla.com
 +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 +L:	linux-samsung-soc@vger.kernel.org
 +S:	Maintained
 +F:	arch/arm64/boot/dts/tesla*
 +
  ARM/TETON BGA MACHINE SUPPORT
  M:	"Mark F. Brown" mark.brown314@gmail.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -3027,7 -3024,7 +3027,7 @@@ L:	linux-media@vger.kernel.or
  L:	openbmc@lists.ozlabs.org (moderated for non-subscribers)
  S:	Maintained
  F:	Documentation/devicetree/bindings/media/aspeed-video.txt
 -F:	drivers/media/platform/aspeed-video.c
 +F:	drivers/media/platform/aspeed/
ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
  M:	Corentin Chary corentin.chary@gmail.com
@@@ -3059,12 -3056,6 +3059,12 @@@ L:	linux-hwmon@vger.kernel.or
  S:	Maintained
  F:	drivers/hwmon/asus_wmi_ec_sensors.c
+ASUS EC HARDWARE MONITOR DRIVER
 +M:	Eugene Shalygin eugene.shalygin@gmail.com
 +L:	linux-hwmon@vger.kernel.org
 +S:	Maintained
 +F:	drivers/hwmon/asus-ec-sensors.c
 +
  ASUS WIRELESS RADIO CONTROL DRIVER
  M:	Jo��o Paulo Rechi Vita jprvita@gmail.com
  L:	platform-driver-x86@vger.kernel.org
@@@ -3207,7 -3198,6 +3207,7 @@@ ATOMIC INFRASTRUCTUR
  M:	Will Deacon will@kernel.org
  M:	Peter Zijlstra peterz@infradead.org
  R:	Boqun Feng boqun.feng@gmail.com
 +R:	Mark Rutland mark.rutland@arm.com
  L:	linux-kernel@vger.kernel.org
  S:	Maintained
  F:	arch/*/include/asm/atomic*.h
@@@ -3389,7 -3379,7 +3389,7 @@@ L:	linux-media@vger.kernel.or
  S:	Supported
  W:	https://linuxtv.org
  T:	git git://linuxtv.org/media_tree.git
 -F:	drivers/media/platform/sti/bdisp
 +F:	drivers/media/platform/st/sti/bdisp
BECKHOFF CX5020 ETHERCAT MASTER DRIVER
  M:	Dariusz Marcinkiewicz reksio@newterm.pl
@@@ -3450,7 -3440,6 +3450,7 @@@ F:	Documentation/ABI/stable/sysfs-bloc
  F:	Documentation/block/
  F:	block/
  F:	drivers/block/
 +F:	include/linux/bio.h
  F:	include/linux/blk*
  F:	kernel/trace/blktrace.c
  F:	lib/sbitmap.c
@@@ -3538,8 -3527,6 +3538,8 @@@ F:	net/sched/act_bpf.
  F:	net/sched/cls_bpf.c
  F:	samples/bpf/
  F:	scripts/bpf_doc.py
 +F:	scripts/pahole-flags.sh
 +F:	scripts/pahole-version.sh
  F:	tools/bpf/
  F:	tools/lib/bpf/
  F:	tools/testing/selftests/bpf/
@@@ -3832,6 -3819,9 +3832,6 @@@ BROADCOM BRCM80211 IEEE802.11n WIRELES
  M:	Arend van Spriel aspriel@gmail.com
  M:	Franky Lin franky.lin@broadcom.com
  M:	Hante Meuleman hante.meuleman@broadcom.com
 -M:	Chi-hsien Lin chi-hsien.lin@infineon.com
 -M:	Wright Feng wright.feng@infineon.com
 -M:	Chung-hsien Hsu chung-hsien.hsu@infineon.com
  L:	linux-wireless@vger.kernel.org
  L:	brcm80211-dev-list.pdl@broadcom.com
  L:	SHA-cyfmac-dev-list@infineon.com
@@@ -3915,7 -3905,7 +3915,7 @@@ M:	Scott Branden <sbranden@broadcom.com
  M:	bcm-kernel-feedback-list@broadcom.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:	Maintained
 -T:	git git://github.com/broadcom/cygnus-linux.git
 +T:	git git://github.com/broadcom/stblinux.git
  F:	arch/arm64/boot/dts/broadcom/northstar2/*
  F:	arch/arm64/boot/dts/broadcom/stingray/*
  F:	drivers/clk/bcm/clk-ns*
@@@ -4253,7 -4243,7 +4253,7 @@@ L:	linux-media@vger.kernel.or
  S:	Orphan
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/admin-guide/media/cafe_ccic*
 -F:	drivers/media/platform/marvell-ccic/
 +F:	drivers/media/platform/marvell/
CAIF NETWORK LAYER
  L:	netdev@vger.kernel.org
@@@ -4777,7 -4767,7 +4777,7 @@@ M:	Philipp Zabel <p.zabel@pengutronix.d
  L:	linux-media@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/media/coda.yaml
 -F:	drivers/media/platform/coda/
 +F:	drivers/media/platform/chips-media/
CODE OF CONDUCT
  M:	Greg Kroah-Hartman gregkh@linuxfoundation.org
@@@ -5327,7 -5317,6 +5327,7 @@@ DATA ACCESS MONITO
  M:	SeongJae Park sj@kernel.org
  L:	linux-mm@kvack.org
  S:	Maintained
 +F:	Documentation/ABI/testing/sysfs-kernel-mm-damon
  F:	Documentation/admin-guide/mm/damon/
  F:	Documentation/vm/damon/
  F:	include/linux/damon.h
@@@ -5421,7 -5410,6 +5421,7 @@@ F:	drivers/platform/x86/dell/dell-rbtn.
  DELL LAPTOP SMM DRIVER
  M:	Pali Roh��r pali@kernel.org
  S:	Maintained
 +F:	Documentation/ABI/obsolete/procfs-i8k
  F:	drivers/hwmon/dell-smm-hwmon.c
  F:	include/uapi/linux/i8k.h
@@@ -5491,7 -5479,7 +5491,7 @@@ L:	linux-media@vger.kernel.or
  S:	Supported
  W:	https://linuxtv.org
  T:	git git://linuxtv.org/media_tree.git
 -F:	drivers/media/platform/sti/delta
 +F:	drivers/media/platform/st/sti/delta
DELTA AHE-50DC FAN CONTROL MODULE DRIVER
  M:	Zev Weiss zev@bewilderbeest.net
@@@ -5751,7 -5739,7 +5751,7 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	Documentation/driver-api/dma-buf.rst
  F:	drivers/dma-buf/
  F:	include/linux/*fence.h
- F:	include/linux/dma-buf*
+ F:	include/linux/dma-buf.h
  F:	include/linux/dma-resv.h
  K:	\bdma_(?:buf|fence|resv)\b
@@@ -6094,7 -6082,8 +6094,8 @@@ L:	dri-devel@lists.freedesktop.or
  T:	git git://anongit.freedesktop.org/drm/drm-misc
  S:	Maintained
  F:	drivers/gpu/drm/panel/panel-lvds.c
- F:	Documentation/devicetree/bindings/display/panel/lvds.yaml
+ F:	Documentation/devicetree/bindings/display/lvds.yaml
+ F:	Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
DRM DRIVER FOR MANTIX MLAF057WE51 PANELS
  M:	Guido G��nther agx@sigxcpu.org
@@@ -6123,6 -6112,14 +6124,14 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt
  F:	drivers/gpu/drm/tiny/mi0283qt.c
+ DRM DRIVER FOR MIPI DBI compatible panels
+ M:	Noralf Tr��nnes noralf@tronnes.org
+ S:	Maintained
+ W:	https://github.com/notro/panel-mipi-dbi/wiki
+ T:	git git://anongit.freedesktop.org/drm/drm-misc
+ F:	Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
+ F:	drivers/gpu/drm/tiny/panel-mipi-dbi.c
+ 
  DRM DRIVER FOR MSM ADRENO GPU
  M:	Rob Clark robdclark@gmail.com
  M:	Sean Paul sean@poorly.run
@@@ -6143,6 -6140,13 +6152,13 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
  F:	drivers/gpu/drm/panel/panel-novatek-nt35510.c
+ DRM DRIVER FOR NOVATEK NT35560 PANELS
+ M:	Linus Walleij linus.walleij@linaro.org
+ S:	Maintained
+ T:	git git://anongit.freedesktop.org/drm/drm-misc
+ F:	Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml
+ F:	drivers/gpu/drm/panel/panel-novatek-nt35560.c
+ 
  DRM DRIVER FOR NOVATEK NT36672A PANELS
  M:	Sumit Semwal sumit.semwal@linaro.org
  S:	Maintained
@@@ -6179,6 -6183,13 +6195,13 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	Documentation/devicetree/bindings/display/repaper.txt
  F:	drivers/gpu/drm/tiny/repaper.c
+ DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
+ M:	Javier Martinez Canillas javierm@redhat.com
+ S:	Maintained
+ T:	git git://anongit.freedesktop.org/drm/drm-misc
+ F:	Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
+ F:	drivers/gpu/drm/solomon/ssd130x*
+ 
  DRM DRIVER FOR QEMU'S CIRRUS DEVICE
  M:	Dave Airlie airlied@redhat.com
  M:	Gerd Hoffmann kraxel@redhat.com
@@@ -6267,12 -6278,6 +6290,6 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	Documentation/devicetree/bindings/display/sitronix,st7735r.yaml
  F:	drivers/gpu/drm/tiny/st7735r.c
- DRM DRIVER FOR SONY ACX424AKP PANELS
- M:	Linus Walleij linus.walleij@linaro.org
- S:	Maintained
- T:	git git://anongit.freedesktop.org/drm/drm-misc
- F:	drivers/gpu/drm/panel/panel-sony-acx424akp.c
- 
  DRM DRIVER FOR ST-ERICSSON MCDE
  M:	Linus Walleij linus.walleij@linaro.org
  S:	Maintained
@@@ -6319,8 -6324,8 +6336,8 @@@ T:	git git://anongit.freedesktop.org/dr
  F:	drivers/gpu/drm/vboxvideo/
DRM DRIVER FOR VMWARE VIRTUAL GPU
 -M:	"VMware Graphics" linux-graphics-maintainer@vmware.com
  M:	Zack Rusin zackr@vmware.com
 +R:	VMware Graphics Reviewers linux-graphics-maintainer@vmware.com
  L:	dri-devel@lists.freedesktop.org
  S:	Supported
  T:	git git://anongit.freedesktop.org/drm/drm-misc
@@@ -7237,9 -7242,6 +7254,9 @@@ F:	net/core/of_net.
  EXEC & BINFMT API
  R:	Eric Biederman ebiederm@xmission.com
  R:	Kees Cook keescook@chromium.org
 +L:	linux-mm@kvack.org
 +S:	Supported
 +T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/execve
  F:	arch/alpha/kernel/binfmt_loader.c
  F:	arch/x86/ia32/ia32_aout.c
  F:	fs/*binfmt_*.c
@@@ -7247,7 -7249,6 +7264,7 @@@ F:	fs/exec.
  F:	include/linux/binfmts.h
  F:	include/linux/elf.h
  F:	include/uapi/linux/binfmts.h
 +F:	include/uapi/linux/elf.h
  F:	tools/testing/selftests/exec/
  N:	asm/elf.h
  N:	binfmt
@@@ -7283,9 -7284,7 +7300,9 @@@ Extended Verification Module (EVM
  M:	Mimi Zohar zohar@linux.ibm.com
  L:	linux-integrity@vger.kernel.org
  S:	Supported
 +T:	git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
  F:	security/integrity/evm/
 +F:	security/integrity/
EXTENSIBLE FIRMWARE INTERFACE (EFI)
  M:	Ard Biesheuvel ardb@kernel.org
@@@ -7762,7 -7761,8 +7779,7 @@@ M:	Qiang Zhao <qiang.zhao@nxp.com
  L:	linuxppc-dev@lists.ozlabs.org
  S:	Maintained
  F:	drivers/soc/fsl/qe/
 -F:	include/soc/fsl/*qe*.h
 -F:	include/soc/fsl/*ucc*.h
 +F:	include/soc/fsl/qe/
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
  M:	Li Yang leoyang.li@nxp.com
@@@ -7793,7 -7793,6 +7810,7 @@@ F:	Documentation/devicetree/bindings/mi
  F:	Documentation/devicetree/bindings/soc/fsl/
  F:	drivers/soc/fsl/
  F:	include/linux/fsl/
 +F:	include/soc/fsl/
FREESCALE SOC FS_ENET DRIVER
  M:	Pantelis Antoniou pantelis.antoniou@gmail.com
@@@ -7804,10 -7803,10 +7821,10 @@@ F:	drivers/net/ethernet/freescale/fs_en
  F:	include/linux/fs_enet_pd.h
FREESCALE SOC SOUND DRIVERS
 -M:	Nicolin Chen nicoleotsuka@gmail.com
 +M:	Shengjiu Wang shengjiu.wang@gmail.com
  M:	Xiubo Li Xiubo.Lee@gmail.com
  R:	Fabio Estevam festevam@gmail.com
 -R:	Shengjiu Wang shengjiu.wang@gmail.com
 +R:	Nicolin Chen nicoleotsuka@gmail.com
  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
  L:	linuxppc-dev@lists.ozlabs.org
  S:	Maintained
@@@ -7948,12 -7947,6 +7965,12 @@@ L:	platform-driver-x86@vger.kernel.or
  S:	Maintained
  F:	drivers/platform/x86/fujitsu-tablet.c
+FUNGIBLE ETHERNET DRIVERS
 +M:	Dimitris Michailidis dmichail@fungible.com
 +L:	netdev@vger.kernel.org
 +S:	Supported
 +F:	drivers/net/ethernet/fungible/
 +
  FUSE: FILESYSTEM IN USERSPACE
  M:	Miklos Szeredi miklos@szeredi.hu
  L:	linux-fsdevel@vger.kernel.org
@@@ -8667,7 -8660,7 +8684,7 @@@ S:	Maintaine
  F:	drivers/gpio/gpio-hisi.c
HISILICON HIGH PERFORMANCE RSA ENGINE DRIVER (HPRE)
 -M:	Zaibo Xu xuzaibo@huawei.com
 +M:	Longfang Liu liulongfang@huawei.com
  L:	linux-crypto@vger.kernel.org
  S:	Maintained
  F:	Documentation/ABI/testing/debugfs-hisi-hpre
@@@ -8727,9 -8720,9 +8744,9 @@@ L:	linux-crypto@vger.kernel.or
  S:	Maintained
  F:	Documentation/ABI/testing/debugfs-hisi-zip
  F:	drivers/crypto/hisilicon/qm.c
 -F:	drivers/crypto/hisilicon/qm.h
  F:	drivers/crypto/hisilicon/sgl.c
  F:	drivers/crypto/hisilicon/zip/
 +F:	include/linux/hisi_acc_qm.h
HISILICON ROCE DRIVER
  M:	Wenpeng Liang liangwenpeng@huawei.com
@@@ -8747,8 -8740,8 +8764,8 @@@ F:	Documentation/devicetree/bindings/sc
  F:	drivers/scsi/hisi_sas/
HISILICON SECURITY ENGINE V2 DRIVER (SEC2)
 -M:	Zaibo Xu xuzaibo@huawei.com
  M:	Kai Ye yekai13@huawei.com
 +M:	Longfang Liu liulongfang@huawei.com
  L:	linux-crypto@vger.kernel.org
  S:	Maintained
  F:	Documentation/ABI/testing/debugfs-hisi-sec
@@@ -8779,7 -8772,7 +8796,7 @@@ F:	Documentation/devicetree/bindings/mf
  F:	drivers/mfd/hi6421-spmi-pmic.c
HISILICON TRUE RANDOM NUMBER GENERATOR V2 SUPPORT
 -M:	Zaibo Xu xuzaibo@huawei.com
 +M:	Weili Qian qianweili@huawei.com
  S:	Maintained
  F:	drivers/crypto/hisilicon/trng/trng.c
@@@ -8893,7 -8886,7 +8910,7 @@@ L:	linux-media@vger.kernel.or
  S:	Supported
  W:	https://linuxtv.org
  T:	git git://linuxtv.org/media_tree.git
 -F:	drivers/media/platform/sti/hva
 +F:	drivers/media/platform/st/sti/hva
HWPOISON MEMORY FAILURE HANDLING
  M:	Naoya Horiguchi naoya.horiguchi@nec.com
@@@ -8928,12 -8921,6 +8945,12 @@@ L:	linux-media@vger.kernel.or
  S:	Maintained
  F:	drivers/media/i2c/hi846.c
+HYNIX HI847 SENSOR DRIVER
 +M:	Shawn Tu shawnx.tu@intel.com
 +L:	linux-media@vger.kernel.org
 +S:	Maintained
 +F:	drivers/media/i2c/hi847.c
 +
  Hyper-V/Azure CORE AND DRIVERS
  M:	"K. Y. Srinivasan" kys@microsoft.com
  M:	Haiyang Zhang haiyangz@microsoft.com
@@@ -9554,7 -9541,6 +9571,7 @@@ L:	linux-integrity@vger.kernel.or
  S:	Supported
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity.git
  F:	security/integrity/ima/
 +F:	security/integrity/
INTEL 810/815 FRAMEBUFFER DRIVER
  M:	Antonino Daplas adaplas@gmail.com
@@@ -10048,14 -10034,6 +10065,14 @@@ L:	linux-iio@vger.kernel.or
  F:	Documentation/devicetree/bindings/counter/interrupt-counter.yaml
  F:	drivers/counter/interrupt-cnt.c
+INTERSIL ISL7998X VIDEO DECODER DRIVER
 +M:	Michael Tretter m.tretter@pengutronix.de
 +R:	Pengutronix Kernel Team kernel@pengutronix.de
 +L:	linux-media@vger.kernel.org
 +S:	Maintained
 +F:	Documentation/devicetree/bindings/media/i2c/isil,isl79987.yaml
 +F:	drivers/media/i2c/isl7998x.c
 +
  INVENSENSE ICM-426xx IMU DRIVER
  M:	Jean-Baptiste Maneyrol jmaneyrol@invensense.com
  L:	linux-iio@vger.kernel.org
@@@ -10103,6 -10081,13 +10120,13 @@@ F:	include/linux/iova.
  F:	include/linux/of_iommu.h
  F:	include/uapi/linux/iommu.h
+ IOSYS-MAP HELPERS
+ M:	Thomas Zimmermann tzimmermann@suse.de
+ L:	dri-devel@lists.freedesktop.org
+ S:	Maintained
+ T:	git git://anongit.freedesktop.org/drm/drm-misc
+ F:	include/linux/iosys-map.h
+ 
  IO_URING
  M:	Jens Axboe axboe@kernel.dk
  R:	Pavel Begunkov asml.silence@gmail.com
@@@ -10355,7 -10340,7 +10379,7 @@@ M:	Mikhail Ulyanov <mikhail.ulyanov@cog
  L:	linux-media@vger.kernel.org
  L:	linux-renesas-soc@vger.kernel.org
  S:	Maintained
 -F:	drivers/media/platform/rcar_jpu.c
 +F:	drivers/media/platform/renesas/rcar_jpu.c
JSM Neo PCI based serial card
  L:	linux-serial@vger.kernel.org
@@@ -10494,8 -10479,6 +10518,8 @@@ KERNEL REGRESSION
  M:	Thorsten Leemhuis linux@leemhuis.info
  L:	regressions@lists.linux.dev
  S:	Supported
 +F:	Documentation/admin-guide/reporting-regressions.rst
 +F:	Documentation/process/handling-regressions.rst
KERNEL SELFTEST FRAMEWORK
  M:	Shuah Khan shuah@kernel.org
@@@ -10603,8 -10586,8 +10627,8 @@@ F:	arch/riscv/kvm
  KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
  M:	Christian Borntraeger borntraeger@linux.ibm.com
  M:	Janosch Frank frankja@linux.ibm.com
 +M:	Claudio Imbrenda imbrenda@linux.ibm.com
  R:	David Hildenbrand david@redhat.com
 -R:	Claudio Imbrenda imbrenda@linux.ibm.com
  L:	kvm@vger.kernel.org
  S:	Supported
  W:	http://www.ibm.com/developerworks/linux/linux390/
@@@ -10701,14 -10684,6 +10725,14 @@@ F:	include/linux/keyctl.
  F:	include/uapi/linux/keyctl.h
  F:	security/keys/
+KEYS/KEYRINGS_INTEGRITY
 +M:	Jarkko Sakkinen jarkko@kernel.org
 +M:	Mimi Zohar zohar@linux.ibm.com
 +L:	linux-integrity@vger.kernel.org
 +L:	keyrings@vger.kernel.org
 +S:	Supported
 +F:	security/integrity/platform_certs
 +
  KFENCE
  M:	Alexander Potapenko glider@google.com
  M:	Marco Elver elver@google.com
@@@ -10814,6 -10789,7 +10838,6 @@@ L7 BPF FRAMEWOR
  M:	John Fastabend john.fastabend@gmail.com
  M:	Daniel Borkmann daniel@iogearbox.net
  M:	Jakub Sitnicki jakub@cloudflare.com
 -M:	Lorenz Bauer lmb@cloudflare.com
  L:	netdev@vger.kernel.org
  L:	bpf@vger.kernel.org
  S:	Maintained
@@@ -11178,17 -11154,12 +11202,17 @@@ F:	lib/list-test.
  LITEX PLATFORM
  M:	Karol Gugala kgugala@antmicro.com
  M:	Mateusz Holenko mholenko@antmicro.com
 +M:	Gabriel Somlo gsomlo@gmail.com
 +M:	Joel Stanley joel@jms.id.au
  S:	Maintained
  F:	Documentation/devicetree/bindings/*/litex,*.yaml
  F:	arch/openrisc/boot/dts/or1klitex.dts
 -F:	drivers/soc/litex/litex_soc_ctrl.c
 -F:	drivers/tty/serial/liteuart.c
  F:	include/linux/litex.h
 +F:	drivers/tty/serial/liteuart.c
 +F:	drivers/soc/litex/*
 +F:	drivers/net/ethernet/litex/*
 +F:	drivers/mmc/host/litex_mmc.c
 +N:	litex
LIVE PATCHING
  M:	Josh Poimboeuf jpoimboe@redhat.com
@@@ -11381,13 -11352,6 +11405,13 @@@ S:	Maintaine
  W:	http://linux-test-project.github.io/
  T:	git git://github.com/linux-test-project/ltp.git
+LYNX 28G SERDES PHY DRIVER
 +M:	Ioana Ciornei ioana.ciornei@nxp.com
 +L:	netdev@vger.kernel.org
 +S:	Supported
 +F:	Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
 +F:	drivers/phy/freescale/phy-fsl-lynx-28g.c
 +
  LYNX PCS MODULE
  M:	Ioana Ciornei ioana.ciornei@nxp.com
  L:	netdev@vger.kernel.org
@@@ -11735,7 -11699,7 +11759,7 @@@ F:	drivers/iio/proximity/mb1232.
MAXIM MAX17040 FAMILY FUEL GAUGE DRIVERS
  R:	Iskren Chernev iskren.chernev@gmail.com
 -R:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +R:	Krzysztof Kozlowski krzk@kernel.org
  R:	Marek Szyprowski m.szyprowski@samsung.com
  R:	Matheus Castello matheus@castello.eng.br
  L:	linux-pm@vger.kernel.org
@@@ -11745,7 -11709,7 +11769,7 @@@ F:	drivers/power/supply/max17040_batter
MAXIM MAX17042 FAMILY FUEL GAUGE DRIVERS
  R:	Hans de Goede hdegoede@redhat.com
 -R:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +R:	Krzysztof Kozlowski krzk@kernel.org
  R:	Marek Szyprowski m.szyprowski@samsung.com
  R:	Sebastian Krzyszkowiak sebastian.krzyszkowiak@puri.sm
  R:	Purism Kernel Team kernel@puri.sm
@@@ -11779,7 -11743,7 +11803,7 @@@ MAXIM MAX77802 PMIC REGULATOR DEVICE DR
  M:	Javier Martinez Canillas javier@dowhile0.org
  L:	linux-kernel@vger.kernel.org
  S:	Supported
 -F:	Documentation/devicetree/bindings/*/*max77802.txt
 +F:	Documentation/devicetree/bindings/*/*max77802.yaml
  F:	drivers/regulator/max77802-regulator.c
  F:	include/dt-bindings/*/*max77802.h
@@@ -11790,26 -11754,23 +11814,26 @@@ F:	Documentation/devicetree/bindings/po
  F:	drivers/power/supply/max77976_charger.c
MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Bartlomiej Zolnierkiewicz b.zolnierkie@samsung.com
  L:	linux-pm@vger.kernel.org
  S:	Supported
 +F:	Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml
  F:	drivers/power/supply/max14577_charger.c
  F:	drivers/power/supply/max77693_charger.c
MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS
  M:	Chanwoo Choi cw00.choi@samsung.com
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Bartlomiej Zolnierkiewicz b.zolnierkie@samsung.com
  L:	linux-kernel@vger.kernel.org
  S:	Supported
 +F:	Documentation/devicetree/bindings/*/maxim,max14577.yaml
  F:	Documentation/devicetree/bindings/*/maxim,max77686.yaml
 +F:	Documentation/devicetree/bindings/*/maxim,max77843.yaml
  F:	Documentation/devicetree/bindings/clock/maxim,max77686.txt
 -F:	Documentation/devicetree/bindings/mfd/max14577.txt
  F:	Documentation/devicetree/bindings/mfd/max77693.txt
 +F:	drivers/*/*max77843.c
  F:	drivers/*/max14577*.c
  F:	drivers/*/max77686*.c
  F:	drivers/*/max77693*.c
@@@ -11905,7 -11866,7 +11929,7 @@@ M:	Philipp Zabel <p.zabel@pengutronix.d
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
 -F:	drivers/media/platform/imx-pxp.[ch]
 +F:	drivers/media/platform/nxp/imx-pxp.[ch]
MEDIA DRIVERS FOR ASCOT2E
  M:	Sergey Kozlov serjk@netup.ru
@@@ -11970,10 -11931,10 +11994,10 @@@ L:	linux-media@vger.kernel.or
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/admin-guide/media/imx7.rst
 +F:	Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
  F:	Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml
 -F:	Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml
 +F:	drivers/media/platform/imx/imx-mipi-csis.c
  F:	drivers/staging/media/imx/imx7-media-csi.c
 -F:	drivers/staging/media/imx/imx7-mipi-csis.c
MEDIA DRIVERS FOR HELENE
  M:	Abylay Ospan aospan@netup.ru
@@@ -12028,7 -11989,7 +12052,7 @@@ L:	linux-tegra@vger.kernel.or
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
 -F:	drivers/staging/media/tegra-vde/
 +F:	drivers/media/platform/nvidia/tegra-vde/
MEDIA DRIVERS FOR RENESAS - CEU
  M:	Jacopo Mondi jacopo@jmondi.org
@@@ -12037,7 -11998,7 +12061,7 @@@ L:	linux-renesas-soc@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/renesas,ceu.yaml
 -F:	drivers/media/platform/renesas-ceu.c
 +F:	drivers/media/platform/renesas/renesas-ceu.c
  F:	include/media/drv-intf/renesas-ceu.h
MEDIA DRIVERS FOR RENESAS - DRIF
@@@ -12047,7 -12008,7 +12071,7 @@@ L:	linux-renesas-soc@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/renesas,drif.yaml
 -F:	drivers/media/platform/rcar_drif.c
 +F:	drivers/media/platform/renesas/rcar_drif.c
MEDIA DRIVERS FOR RENESAS - FCP
  M:	Laurent Pinchart laurent.pinchart@ideasonboard.com
@@@ -12056,7 -12017,7 +12080,7 @@@ L:	linux-renesas-soc@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/renesas,fcp.yaml
 -F:	drivers/media/platform/rcar-fcp.c
 +F:	drivers/media/platform/renesas/rcar-fcp.c
  F:	include/media/rcar-fcp.h
MEDIA DRIVERS FOR RENESAS - FDP1
@@@ -12066,7 -12027,7 +12090,7 @@@ L:	linux-renesas-soc@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/renesas,fdp1.yaml
 -F:	drivers/media/platform/rcar_fdp1.c
 +F:	drivers/media/platform/renesas/rcar_fdp1.c
MEDIA DRIVERS FOR RENESAS - VIN
  M:	Niklas S��derlund niklas.soderlund@ragnatech.se
@@@ -12077,8 -12038,8 +12101,8 @@@ T:	git git://linuxtv.org/media_tree.gi
  F:	Documentation/devicetree/bindings/media/renesas,csi2.yaml
  F:	Documentation/devicetree/bindings/media/renesas,isp.yaml
  F:	Documentation/devicetree/bindings/media/renesas,vin.yaml
 -F:	drivers/media/platform/rcar-isp.c
 -F:	drivers/media/platform/rcar-vin/
 +F:	drivers/media/platform/renesas/rcar-isp.c
 +F:	drivers/media/platform/renesas/rcar-vin/
MEDIA DRIVERS FOR RENESAS - VSP1
  M:	Laurent Pinchart laurent.pinchart@ideasonboard.com
@@@ -12088,7 -12049,7 +12112,7 @@@ L:	linux-renesas-soc@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/renesas,vsp1.yaml
 -F:	drivers/media/platform/vsp1/
 +F:	drivers/media/platform/renesas/vsp1/
MEDIA DRIVERS FOR ST STV0910 DEMODULATOR ICs
  L:	linux-media@vger.kernel.org
@@@ -12110,7 -12071,7 +12134,7 @@@ L:	linux-media@vger.kernel.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
 -F:	drivers/media/platform/stm32/stm32-dcmi.c
 +F:	drivers/media/platform/st/stm32/stm32-dcmi.c
MEDIA INPUT INFRASTRUCTURE (V4L/DVB)
  M:	Mauro Carvalho Chehab mchehab@kernel.org
@@@ -12194,7 -12155,7 +12218,7 @@@ M:	Rick Chang <rick.chang@mediatek.com
  M:	Bin Liu bin.liu@mediatek.com
  S:	Supported
  F:	Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
 -F:	drivers/media/platform/mtk-jpeg/
 +F:	drivers/media/platform/mediatek/jpeg/
MEDIATEK MDP DRIVER
  M:	Minghsiu Tsai minghsiu.tsai@mediatek.com
@@@ -12202,8 -12163,8 +12226,8 @@@ M:	Houlong Wei <houlong.wei@mediatek.co
  M:	Andrew-CT Chen andrew-ct.chen@mediatek.com
  S:	Supported
  F:	Documentation/devicetree/bindings/media/mediatek-mdp.txt
 -F:	drivers/media/platform/mtk-mdp/
 -F:	drivers/media/platform/mtk-vpu/
 +F:	drivers/media/platform/mediatek/mdp/
 +F:	drivers/media/platform/mediatek/vpu/
MEDIATEK MEDIA DRIVER
  M:	Tiffany Lin tiffany.lin@mediatek.com
@@@ -12211,8 -12172,8 +12235,8 @@@ M:	Andrew-CT Chen <andrew-ct.chen@media
  S:	Supported
  F:	Documentation/devicetree/bindings/media/mediatek-vcodec.txt
  F:	Documentation/devicetree/bindings/media/mediatek-vpu.txt
 -F:	drivers/media/platform/mtk-vcodec/
 -F:	drivers/media/platform/mtk-vpu/
 +F:	drivers/media/platform/mediatek/vcodec/
 +F:	drivers/media/platform/mediatek/vpu/
MEDIATEK MMC/SD/SDIO DRIVER
  M:	Chaotian Jing chaotian.jing@mediatek.com
@@@ -12228,7 -12189,6 +12252,7 @@@ R:	Shayne Chen <shayne.chen@mediatek.co
  R:	Sean Wang sean.wang@mediatek.com
  L:	linux-wireless@vger.kernel.org
  S:	Maintained
 +F:	Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml
  F:	drivers/net/wireless/mediatek/mt76/
MEDIATEK MT7601U WIRELESS LAN DRIVER
@@@ -12492,7 -12452,7 +12516,7 @@@ F:	include/linux/memblock.
  F:	mm/memblock.c
MEMORY CONTROLLER DRIVERS
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-kernel@vger.kernel.org
  S:	Maintained
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
@@@ -12588,7 -12548,7 +12612,7 @@@ L:	linux-amlogic@lists.infradead.or
  S:	Supported
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/amlogic,axg-ge2d.yaml
 -F:	drivers/media/platform/meson/ge2d/
 +F:	drivers/media/platform/amlogic/meson-ge2d/
MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS
  M:	Liang Yang liang.yang@amlogic.com
@@@ -12670,13 -12630,6 +12694,13 @@@ L:	alsa-devel@alsa-project.org (moderat
  S:	Supported
  F:	sound/soc/atmel
+MICROCHIP CSI2DC DRIVER
 +M:	Eugen Hristev eugen.hristev@microchip.com
 +L:	linux-media@vger.kernel.org
 +S:	Supported
 +F:	Documentation/devicetree/bindings/media/microchip,csi2dc.yaml
 +F:	drivers/media/platform/atmel/microchip-csi2dc.c
 +
  MICROCHIP ECC DRIVER
  M:	Tudor Ambarus tudor.ambarus@microchip.com
  L:	linux-crypto@vger.kernel.org
@@@ -12702,8 -12655,11 +12726,8 @@@ L:	linux-media@vger.kernel.or
  S:	Supported
  F:	Documentation/devicetree/bindings/media/atmel,isc.yaml
  F:	Documentation/devicetree/bindings/media/microchip,xisc.yaml
 -F:	drivers/media/platform/atmel/atmel-isc-base.c
 -F:	drivers/media/platform/atmel/atmel-isc-regs.h
 -F:	drivers/media/platform/atmel/atmel-isc.h
 -F:	drivers/media/platform/atmel/atmel-sama5d2-isc.c
 -F:	drivers/media/platform/atmel/atmel-sama7g5-isc.c
 +F:	drivers/media/platform/atmel/atmel-isc*
 +F:	drivers/media/platform/atmel/atmel-sama*-isc*
  F:	include/linux/atmel-isc-media.h
MICROCHIP ISI DRIVER
@@@ -13444,7 -13400,6 +13468,7 @@@ F:	net/core/drop_monitor.
  NETWORKING DRIVERS
  M:	"David S. Miller" davem@davemloft.net
  M:	Jakub Kicinski kuba@kernel.org
 +M:	Paolo Abeni pabeni@redhat.com
  L:	netdev@vger.kernel.org
  S:	Maintained
  Q:	https://patchwork.kernel.org/project/netdevbpf/list/
@@@ -13491,7 -13446,6 +13515,7 @@@ F:	tools/testing/selftests/drivers/net/
  NETWORKING [GENERAL]
  M:	"David S. Miller" davem@davemloft.net
  M:	Jakub Kicinski kuba@kernel.org
 +M:	Paolo Abeni pabeni@redhat.com
  L:	netdev@vger.kernel.org
  S:	Maintained
  Q:	https://patchwork.kernel.org/project/netdevbpf/list/
@@@ -13635,7 -13589,7 +13659,7 @@@ F:	include/uapi/linux/nexthop.
  F:	net/ipv4/nexthop.c
NFC SUBSYSTEM
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-nfc@lists.01.org (subscribers-only)
  L:	netdev@vger.kernel.org
  S:	Maintained
@@@ -13769,7 -13723,7 +13793,7 @@@ F:	scripts/nsdep
  NTB AMD DRIVER
  M:	Sanjay R Mehta sanju.mehta@amd.com
  M:	Shyam Sundar S K Shyam-sundar.S-k@amd.com
 -L:	linux-ntb@googlegroups.com
 +L:	ntb@lists.linux.dev
  S:	Supported
  F:	drivers/ntb/hw/amd/
@@@ -13777,7 -13731,7 +13801,7 @@@ NTB DRIVER COR
  M:	Jon Mason jdmason@kudzu.us
  M:	Dave Jiang dave.jiang@intel.com
  M:	Allen Hubbe allenbh@gmail.com
 -L:	linux-ntb@googlegroups.com
 +L:	ntb@lists.linux.dev
  S:	Supported
  W:	https://github.com/jonmason/ntb/wiki
  T:	git git://github.com/jonmason/ntb.git
@@@ -13789,13 -13743,13 +13813,13 @@@ F:	tools/testing/selftests/ntb
NTB IDT DRIVER
  M:	Serge Semin fancer.lancer@gmail.com
 -L:	linux-ntb@googlegroups.com
 +L:	ntb@lists.linux.dev
  S:	Supported
  F:	drivers/ntb/hw/idt/
NTB INTEL DRIVER
  M:	Dave Jiang dave.jiang@intel.com
 -L:	linux-ntb@googlegroups.com
 +L:	ntb@lists.linux.dev
  S:	Supported
  W:	https://github.com/davejiang/linux/wiki
  T:	git https://github.com/davejiang/linux.git
@@@ -13949,7 -13903,7 +13973,7 @@@ F:	Documentation/devicetree/bindings/re
  F:	drivers/regulator/pf8x00-regulator.c
NXP PTN5150A CC LOGIC AND EXTCON DRIVER
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-kernel@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/extcon/extcon-ptn5150.yaml
@@@ -14162,7 -14116,7 +14186,7 @@@ M:	Laurent Pinchart <laurent.pinchart@i
  L:	linux-media@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/media/ti,omap3isp.txt
 -F:	drivers/media/platform/omap3isp/
 +F:	drivers/media/platform/ti/omap3isp/
  F:	drivers/staging/media/omap4iss/
OMAP MMC SUPPORT
@@@ -14270,12 -14224,6 +14294,12 @@@ M:	Harald Welte <laforge@gnumonks.org
  S:	Maintained
  F:	drivers/char/pcmcia/cm4040_cs.*
+OMNIVISION OG01A1B SENSOR DRIVER
 +M:	Shawn Tu shawnx.tu@intel.com
 +L:	linux-media@vger.kernel.org
 +S:	Maintained
 +F:	drivers/media/i2c/og01a1b.c
 +
  OMNIVISION OV02A10 SENSOR DRIVER
  M:	Dongchun Zhu dongchun.zhu@mediatek.com
  L:	linux-media@vger.kernel.org
@@@ -14284,13 -14232,6 +14308,13 @@@ T:	git git://linuxtv.org/media_tree.gi
  F:	Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
  F:	drivers/media/i2c/ov02a10.c
+OMNIVISION OV08D10 SENSOR DRIVER
 +M:	Jimmy Su jimmy.su@intel.com
 +L:	linux-media@vger.kernel.org
 +S:	Maintained
 +T:	git git://linuxtv.org/media_tree.git
 +F:	drivers/media/i2c/ov08d10.c
 +
  OMNIVISION OV13858 SENSOR DRIVER
  M:	Sakari Ailus sakari.ailus@linux.intel.com
  L:	linux-media@vger.kernel.org
@@@ -14686,9 -14627,8 +14710,9 @@@ F:	include/uapi/linux/ppdev.
PARAVIRT_OPS INTERFACE
  M:	Juergen Gross jgross@suse.com
 -M:	Deep Shah sdeep@vmware.com
 -M:	"VMware, Inc." pv-drivers@vmware.com
 +M:	Srivatsa S. Bhat (VMware) srivatsa@csail.mit.edu
 +R:	Alexey Makhalov amakhalov@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	virtualization@lists.linux-foundation.org
  L:	x86@kernel.org
  S:	Supported
@@@ -15389,7 -15329,7 +15413,7 @@@ F:	drivers/pinctrl/renesas
PIN CONTROLLER - SAMSUNG
  M:	Tomasz Figa tomasz.figa@gmail.com
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Sylwester Nawrocki s.nawrocki@samsung.com
  R:	Alim Akhtar alim.akhtar@samsung.com
  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -15398,7 -15338,7 +15422,7 @@@ S:	Maintaine
  C:	irc://irc.libera.chat/linux-exynos
  Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
 -F:	Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
 +F:	Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml
  F:	drivers/pinctrl/samsung/
  F:	include/dt-bindings/pinctrl/samsung.h
@@@ -15617,7 -15557,6 +15641,7 @@@ F:	drivers/net/ppp/pptp.
PRESSURE STALL INFORMATION (PSI)
  M:	Johannes Weiner hannes@cmpxchg.org
 +M:	Suren Baghdasaryan surenb@google.com
  S:	Maintained
  F:	include/linux/psi*
  F:	kernel/sched/psi.c
@@@ -16008,8 -15947,8 +16032,8 @@@ M:	Kalle Valo <kvalo@kernel.org
  L:	ath11k@lists.infradead.org
  S:	Supported
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
 +F:	Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
  F:	drivers/net/wireless/ath/ath11k/
 -F:	Documentation/devicetree/bindings/net/wireless/qcom,ath11k.txt
QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
  M:	Toke H��iland-J��rgensen toke@toke.dk
@@@ -16292,7 -16231,6 +16316,7 @@@ M:	Jason A. Donenfeld <Jason@zx2c4.com
  T:	git https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git
  S:	Maintained
  F:	drivers/char/random.c
 +F:	drivers/virt/vmgenid.c
RAPIDIO SUBSYSTEM
  M:	Matt Porter mporter@kernel.crashing.org
@@@ -16407,8 -16345,6 +16431,8 @@@ F:	tools/testing/selftests/resctrl
READ-COPY UPDATE (RCU)
  M:	"Paul E. McKenney" paulmck@kernel.org
 +M:	Frederic Weisbecker frederic@kernel.org (kernel/rcu/tree_nocb.h)
 +M:	Neeraj Upadhyay quic_neeraju@quicinc.com (kernel/rcu/tasks.h)
  M:	Josh Triplett josh@joshtriplett.org
  R:	Steven Rostedt rostedt@goodmis.org
  R:	Mathieu Desnoyers mathieu.desnoyers@efficios.com
@@@ -16458,8 -16394,9 +16482,8 @@@ REALTEK RTL83xx SMI DSA ROUTER CHIP
  M:	Linus Walleij linus.walleij@linaro.org
  M:	Alvin ��ipraga alsi@bang-olufsen.dk
  S:	Maintained
 -F:	Documentation/devicetree/bindings/net/dsa/realtek-smi.txt
 -F:	drivers/net/dsa/realtek-smi*
 -F:	drivers/net/dsa/rtl83*
 +F:	Documentation/devicetree/bindings/net/dsa/realtek.yaml
 +F:	drivers/net/dsa/realtek/*
REALTEK WIRELESS DRIVER (rtlwifi family)
  M:	Ping-Ke Shih pkshih@realtek.com
@@@ -16724,7 -16661,8 +16748,7 @@@ F:	Documentation/devicetree/bindings/so
  F:	sound/soc/rockchip/rockchip_i2s_tdm.*
ROCKCHIP ISP V1 DRIVER
 -M:	Helen Koike helen.koike@collabora.com
 -M:	Dafna Hirschfeld dafna.hirschfeld@collabora.com
 +M:	Dafna Hirschfeld dafna@fastmail.com
  L:	linux-media@vger.kernel.org
  L:	linux-rockchip@lists.infradead.org
  S:	Maintained
@@@ -17033,7 -16971,7 +17057,7 @@@ W:	http://www.ibm.com/developerworks/li
  F:	drivers/s390/scsi/zfcp_*
S3C ADC BATTERY DRIVER
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-samsung-soc@vger.kernel.org
  S:	Odd Fixes
  F:	drivers/power/supply/s3c_adc_battery.c
@@@ -17078,7 -17016,7 +17102,7 @@@ F:	Documentation/admin-guide/LSM/SafeSe
  F:	security/safesetid/
SAMSUNG AUDIO (ASoC) DRIVERS
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Sylwester Nawrocki s.nawrocki@samsung.com
  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
  S:	Supported
@@@ -17086,7 -17024,7 +17110,7 @@@ F:	Documentation/devicetree/bindings/so
  F:	sound/soc/samsung/
SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-crypto@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
  S:	Maintained
@@@ -17121,7 -17059,7 +17145,7 @@@ S:	Maintaine
  F:	drivers/platform/x86/samsung-laptop.c
SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Bartlomiej Zolnierkiewicz b.zolnierkie@samsung.com
  L:	linux-kernel@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
@@@ -17143,11 -17081,11 +17167,11 @@@ M:	Sylwester Nawrocki <sylvester.nawroc
  L:	linux-media@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
  S:	Maintained
 -F:	drivers/media/platform/s3c-camif/
 +F:	drivers/media/platform/samsung/s3c-camif/
  F:	include/media/drv-intf/s3c_camif.h
SAMSUNG S3FWRN5 NFC DRIVER
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Krzysztof Opasiak k.opasiak@samsung.com
  L:	linux-nfc@lists.01.org (subscribers-only)
  S:	Maintained
@@@ -17169,7 -17107,7 +17193,7 @@@ S:	Supporte
  F:	drivers/media/i2c/s5k5baf.c
SAMSUNG S5P Security SubSystem (SSS) DRIVER
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Vladimir Zapolskiy vz@mleia.com
  L:	linux-crypto@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
@@@ -17183,7 -17121,7 +17207,7 @@@ M:	Sylwester Nawrocki <s.nawrocki@samsu
  L:	linux-media@vger.kernel.org
  S:	Supported
  Q:	https://patchwork.linuxtv.org/project/linux-media/list/
 -F:	drivers/media/platform/exynos4-is/
 +F:	drivers/media/platform/samsung/exynos4-is/
SAMSUNG SOC CLOCK DRIVERS
  M:	Sylwester Nawrocki s.nawrocki@samsung.com
@@@ -17204,12 -17142,12 +17228,12 @@@ F:	include/linux/clk/samsung.
  F:	include/linux/platform_data/clk-s3c2410.h
SAMSUNG SPI DRIVERS
 -M:	Krzysztof Kozlowski krzysztof.kozlowski@canonical.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  M:	Andi Shyti andi@etezian.org
  L:	linux-spi@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
  S:	Maintained
 -F:	Documentation/devicetree/bindings/spi/spi-samsung.txt
 +F:	Documentation/devicetree/bindings/spi/samsung,spi*.yaml
  F:	drivers/spi/spi-s3c*
  F:	include/linux/platform_data/spi-s3c64xx.h
  F:	include/linux/spi/s3c24xx-fiq.h
@@@ -17221,12 -17159,11 +17245,12 @@@ S:	Supporte
  F:	drivers/net/ethernet/samsung/sxgbe/
SAMSUNG THERMAL DRIVER
 -M:	Bartlomiej Zolnierkiewicz b.zolnierkie@samsung.com
 +M:	Bartlomiej Zolnierkiewicz bzolnier@gmail.com
 +M:	Krzysztof Kozlowski krzk@kernel.org
  L:	linux-pm@vger.kernel.org
  L:	linux-samsung-soc@vger.kernel.org
 -S:	Supported
 -T:	git https://github.com/lmajewski/linux-samsung-thermal.git
 +S:	Maintained
 +F:	Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml
  F:	drivers/thermal/samsung/
SAMSUNG USB2 PHY DRIVER
@@@ -17618,7 -17555,7 +17642,7 @@@ F:	include/media/i2c/rj54n1cb0c.
  SH_VOU V4L2 OUTPUT DRIVER
  L:	linux-media@vger.kernel.org
  S:	Orphan
 -F:	drivers/media/platform/sh_vou.c
 +F:	drivers/media/platform/renesas/sh_vou.c
  F:	include/media/drv-intf/sh_vou.h
SI2157 MEDIA DRIVER
@@@ -18390,8 -18327,7 +18414,8 @@@ F:	Documentation/devicetree/bindings/ii
  F:	drivers/iio/imu/st_lsm6dsx/
ST MIPID02 CSI-2 TO PARALLEL BRIDGE DRIVER
 -M:	Mickael Guene mickael.guene@st.com
 +M:	Benjamin Mugnier benjamin.mugnier@foss.st.com
 +M:	Sylvain Petinot sylvain.petinot@foss.st.com
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
@@@ -18630,13 -18566,6 +18654,13 @@@ S:	Maintaine
  F:	Documentation/devicetree/bindings/rtc/sunplus,sp7021-rtc.yaml
  F:	drivers/rtc/rtc-sunplus.c
+SUNPLUS SPI CONTROLLER INTERFACE DRIVER
 +M:	Li-hao Kuo lhjeff911@gmail.com
 +L:	linux-spi@vger.kernel.org
 +S:	Maintained
 +F:	Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml
 +F:	drivers/spi/spi-sunplus-sp7021.c
 +
  SUPERH
  M:	Yoshinori Sato ysato@users.sourceforge.jp
  M:	Rich Felker dalias@libc.org
@@@ -19188,7 -19117,6 +19212,7 @@@ TEXAS INSTRUMENTS ASoC DRIVER
  M:	Peter Ujfalusi peter.ujfalusi@gmail.com
  L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
  S:	Maintained
 +F:	Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml
  F:	sound/soc/ti/
TEXAS INSTRUMENTS' DAC7612 DAC DRIVER
@@@ -19369,7 -19297,7 +19393,7 @@@ S:	Maintaine
  W:	https://linuxtv.org
  Q:	http://patchwork.linuxtv.org/project/linux-media/list/
  T:	git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git
 -F:	drivers/media/platform/am437x/
 +F:	drivers/media/platform/ti/am437x/
TI BANDGAP AND THERMAL DRIVER
  M:	Eduardo Valentin edubezval@gmail.com
@@@ -19428,7 -19356,7 +19452,7 @@@ S:	Maintaine
  W:	https://linuxtv.org
  Q:	http://patchwork.linuxtv.org/project/linux-media/list/
  T:	git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git
 -F:	drivers/media/platform/davinci/
 +F:	drivers/media/platform/ti/davinci/
  F:	include/media/davinci/
TI ENHANCED QUADRATURE ENCODER PULSE (eQEP) DRIVER
@@@ -19514,8 -19442,7 +19538,8 @@@ W:	http://linuxtv.org
  Q:	http://patchwork.linuxtv.org/project/linux-media/list/
  F:	Documentation/devicetree/bindings/media/ti,cal.yaml
  F:	Documentation/devicetree/bindings/media/ti,vpe.yaml
 -F:	drivers/media/platform/ti-vpe/
 +F:	drivers/media/platform/ti/cal/
 +F:	drivers/media/platform/ti/vpe/
TI WILINK WIRELESS DRIVERS
  L:	linux-wireless@vger.kernel.org
@@@ -19586,15 -19513,6 +19610,15 @@@ S:	Maintaine
  F:	Documentation/hwmon/tmp401.rst
  F:	drivers/hwmon/tmp401.c
+TMP464 HARDWARE MONITOR DRIVER
 +M:	Agathe Porte agathe.porte@nokia.com
 +M:	Guenter Roeck linux@roeck-us.net
 +L:	linux-hwmon@vger.kernel.org
 +S:	Maintained
 +F:	Documentation/devicetree/bindings/hwmon/ti,tmp464.yaml
 +F:	Documentation/hwmon/tmp464.rst
 +F:	drivers/hwmon/tmp464.c
 +
  TMP513 HARDWARE MONITOR DRIVER
  M:	Eric Tremblay etremblay@distech-controls.com
  L:	linux-hwmon@vger.kernel.org
@@@ -20410,13 -20328,6 +20434,13 @@@ L:	kvm@vger.kernel.or
  S:	Maintained
  F:	drivers/vfio/fsl-mc/
+VFIO HISILICON PCI DRIVER
 +M:	Longfang Liu liulongfang@huawei.com
 +M:	Shameer Kolothum shameerali.kolothum.thodi@huawei.com
 +L:	kvm@vger.kernel.org
 +S:	Maintained
 +F:	drivers/vfio/pci/hisilicon/
 +
  VFIO MEDIATED DEVICE DRIVERS
  M:	Kirti Wankhede kwankhede@nvidia.com
  L:	kvm@vger.kernel.org
@@@ -20426,28 -20337,12 +20450,28 @@@ F:	drivers/vfio/mdev
  F:	include/linux/mdev.h
  F:	samples/vfio-mdev/
+VFIO PCI DEVICE SPECIFIC DRIVERS
 +R:	Jason Gunthorpe jgg@nvidia.com
 +R:	Yishai Hadas yishaih@nvidia.com
 +R:	Shameer Kolothum shameerali.kolothum.thodi@huawei.com
 +R:	Kevin Tian kevin.tian@intel.com
 +L:	kvm@vger.kernel.org
 +S:	Maintained
 +P:	Documentation/driver-api/vfio-pci-device-specific-driver-acceptance.rst
 +F:	drivers/vfio/pci/*/
 +
  VFIO PLATFORM DRIVER
  M:	Eric Auger eric.auger@redhat.com
  L:	kvm@vger.kernel.org
  S:	Maintained
  F:	drivers/vfio/platform/
+VFIO MLX5 PCI DRIVER
 +M:	Yishai Hadas yishaih@nvidia.com
 +L:	kvm@vger.kernel.org
 +S:	Maintained
 +F:	drivers/vfio/pci/mlx5/
 +
  VGA_SWITCHEROO
  R:	Lukas Wunner lukas@wunner.de
  S:	Maintained
@@@ -20511,8 -20406,8 +20535,8 @@@ F:	drivers/media/common/videobuf2/
  F:	include/media/videobuf2-*
VIMC VIRTUAL MEDIA CONTROLLER DRIVER
 -M:	Helen Koike helen.koike@collabora.com
 -R:	Shuah Khan skhan@linuxfoundation.org
 +M:	Shuah Khan skhan@linuxfoundation.org
 +R:	Kieran Bingham kieran.bingham@ideasonboard.com
  L:	linux-media@vger.kernel.org
  S:	Maintained
  W:	https://linuxtv.org
@@@ -20767,33 -20662,30 +20791,33 @@@ F:	tools/testing/vsock
VMWARE BALLOON DRIVER
  M:	Nadav Amit namit@vmware.com
 -M:	"VMware, Inc." pv-drivers@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	linux-kernel@vger.kernel.org
  S:	Maintained
  F:	drivers/misc/vmw_balloon.c
VMWARE HYPERVISOR INTERFACE
 -M:	Deep Shah sdeep@vmware.com
 -M:	"VMware, Inc." pv-drivers@vmware.com
 +M:	Srivatsa S. Bhat (VMware) srivatsa@csail.mit.edu
 +M:	Alexey Makhalov amakhalov@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	virtualization@lists.linux-foundation.org
 +L:	x86@kernel.org
  S:	Supported
 +T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/vmware
  F:	arch/x86/include/asm/vmware.h
  F:	arch/x86/kernel/cpu/vmware.c
VMWARE PVRDMA DRIVER
  M:	Bryan Tan bryantan@vmware.com
  M:	Vishnu Dasa vdasa@vmware.com
 -M:	VMware PV-Drivers pv-drivers@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	linux-rdma@vger.kernel.org
  S:	Maintained
  F:	drivers/infiniband/hw/vmw_pvrdma/
VMware PVSCSI driver
  M:	Vishal Bhakta vbhakta@vmware.com
 -M:	VMware PV-Drivers pv-drivers@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	linux-scsi@vger.kernel.org
  S:	Maintained
  F:	drivers/scsi/vmw_pvscsi.c
@@@ -20801,7 -20693,7 +20825,7 @@@ F:	drivers/scsi/vmw_pvscsi.
VMWARE VIRTUAL PTP CLOCK DRIVER
  M:	Vivek Thampi vithampi@vmware.com
 -M:	"VMware, Inc." pv-drivers@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	netdev@vger.kernel.org
  S:	Supported
  F:	drivers/ptp/ptp_vmw.c
@@@ -20809,15 -20701,14 +20833,15 @@@
  VMWARE VMCI DRIVER
  M:	Jorgen Hansen jhansen@vmware.com
  M:	Vishnu Dasa vdasa@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	linux-kernel@vger.kernel.org
 -L:	pv-drivers@vmware.com (private)
  S:	Maintained
  F:	drivers/misc/vmw_vmci/
VMWARE VMMOUSE SUBDRIVER
 -M:	"VMware Graphics" linux-graphics-maintainer@vmware.com
 -M:	"VMware, Inc." pv-drivers@vmware.com
 +M:	Zack Rusin zackr@vmware.com
 +R:	VMware Graphics Reviewers linux-graphics-maintainer@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	linux-input@vger.kernel.org
  S:	Maintained
  F:	drivers/input/mouse/vmmouse.c
@@@ -20825,7 -20716,7 +20849,7 @@@ F:	drivers/input/mouse/vmmouse.
VMWARE VMXNET3 ETHERNET DRIVER
  M:	Ronak Doshi doshir@vmware.com
 -M:	pv-drivers@vmware.com
 +R:	VMware PV-Drivers Reviewers pv-drivers@vmware.com
  L:	netdev@vger.kernel.org
  S:	Maintained
  F:	drivers/net/vmxnet3/
@@@ -21201,7 -21092,7 +21225,7 @@@ L:	linux-media@vger.kernel.or
  S:	Maintained
  W:	https://linuxtv.org
  T:	git git://linuxtv.org/media_tree.git
 -F:	drivers/media/tuners/tuner-xc2028.*
 +F:	drivers/media/tuners/xc2028.*
XDP (eXpress Data Path)
  M:	Alexei Starovoitov ast@kernel.org
@@@ -21421,11 -21312,6 +21445,11 @@@ T:	git https://github.com/Xilinx/linux-
  F:	Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
  F:	drivers/phy/xilinx/phy-zynqmp.c
+XILINX ZYNQMP SHA3 DRIVER
 +M:	Harsha harsha.harsha@xilinx.com
 +S:	Maintained
 +F:	drivers/crypto/xilinx/zynqmp-sha.c
 +
  XILINX EVENT MANAGEMENT DRIVER
  M:	Abhyuday Godhasara abhyuday.godhasara@xilinx.com
  S:	Maintained
@@@ -21606,6 -21492,7 +21630,6 @@@ THE RES
  M:	Linus Torvalds torvalds@linux-foundation.org
  L:	linux-kernel@vger.kernel.org
  S:	Buried alive in reporters
 -Q:	http://patchwork.kernel.org/project/LKML/list/
  T:	git git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
  F:	*
  F:	*/
diff --combined drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index e27ca3758762,3a29d857640b..7e3a7fcb9fe6
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@@ -24,7 -24,6 +24,7 @@@
  #include <linux/hmm.h>
  #include <linux/dma-direction.h>
  #include <linux/dma-mapping.h>
 +#include <linux/migrate.h>
  #include "amdgpu_sync.h"
  #include "amdgpu_object.h"
  #include "amdgpu_vm.h"
@@@ -37,7 -36,7 +37,7 @@@
  #ifdef dev_fmt
  #undef dev_fmt
  #endif
- #define dev_fmt(fmt) "kfd_migrate: %s: " fmt, __func__
+ #define dev_fmt(fmt) "kfd_migrate: " fmt
static uint64_t
  svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, uint64_t addr)
@@@ -87,10 -86,7 +87,7 @@@ svm_migrate_gart_map(struct amdgpu_rin
cpu_addr = &job->ibs[0].ptr[num_dw];
- 	r = amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr);
- 	if (r)
- 		goto error_free;
- 
+ 	amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr);
    r = amdgpu_job_submit(job, &adev->mman.entity,
    		      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
    if (r)
@@@ -225,6 -221,7 +222,6 @@@ svm_migrate_get_vram_page(struct svm_ra
    page = pfn_to_page(pfn);
    svm_range_bo_ref(prange->svm_bo);
    page->zone_device_data = prange->svm_bo;
 -	get_page(page);
    lock_page(page);
  }
@@@ -315,7 -312,7 +312,7 @@@ svm_migrate_copy_to_vram(struct amdgpu_
r = svm_range_vram_node_new(adev, prange, true);
    if (r) {
- 		dev_err(adev->dev, "fail %d to alloc vram\n", r);
+ 		dev_dbg(adev->dev, "fail %d to alloc vram\n", r);
    	goto out;
    }
@@@ -334,7 -331,8 +331,8 @@@
    				      DMA_TO_DEVICE);
    		r = dma_mapping_error(dev, src[i]);
    		if (r) {
- 				dev_err(adev->dev, "fail %d dma_map_page\n", r);
+ 				dev_err(adev->dev, "%s: fail %d dma_map_page\n",
+ 					__func__, r);
    			goto out_free_vram_pages;
    		}
    	} else {
@@@ -365,7 -363,7 +363,7 @@@
    		if (r)
    			goto out_free_vram_pages;
    		amdgpu_res_next(&cursor, (j + 1) * PAGE_SIZE);
- 			j= 0;
+ 			j = 0;
    	} else {
    		j++;
    	}
@@@ -435,8 -433,8 +433,8 @@@ svm_migrate_vma_to_vram(struct amdgpu_d
r = migrate_vma_setup(&migrate);
    if (r) {
- 		dev_err(adev->dev, "vma setup fail %d range [0x%lx 0x%lx]\n", r,
- 			prange->start, prange->last);
+ 		dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n",
+ 			__func__, r, prange->start, prange->last);
    	goto out_free;
    }
@@@ -614,7 -612,7 +612,7 @@@ svm_migrate_copy_to_ram(struct amdgpu_d
    	dst[i] = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_FROM_DEVICE);
    	r = dma_mapping_error(dev, dst[i]);
    	if (r) {
- 			dev_err(adev->dev, "fail %d dma_map_page\n", r);
+ 			dev_err(adev->dev, "%s: fail %d dma_map_page\n", __func__, r);
    		goto out_oom;
    	}
@@@ -640,6 -638,22 +638,22 @@@ out_oom
    return r;
  }
+ /**
+  * svm_migrate_vma_to_ram - migrate range inside one vma from device to system
+  *
+  * @adev: amdgpu device to migrate from
+  * @prange: svm range structure
+  * @vma: vm_area_struct that range [start, end] belongs to
+  * @start: range start virtual address in pages
+  * @end: range end virtual address in pages
+  *
+  * Context: Process context, caller hold mmap read lock, prange->migrate_mutex
+  *
+  * Return:
+  *   0 - success with all pages migrated
+  *   negative values - indicate error
+  *   positive values - partial migration, number of pages not migrated
+  */
  static long
  svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
    	       struct vm_area_struct *vma, uint64_t start, uint64_t end)
@@@ -674,8 -688,8 +688,8 @@@
r = migrate_vma_setup(&migrate);
    if (r) {
- 		dev_err(adev->dev, "vma setup fail %d range [0x%lx 0x%lx]\n", r,
- 			prange->start, prange->last);
+ 		dev_err(adev->dev, "%s: vma setup fail %d range [0x%lx 0x%lx]\n",
+ 			__func__, r, prange->start, prange->last);
    	goto out_free;
    }
@@@ -711,8 -725,6 +725,6 @@@ out
    	pdd = svm_range_get_pdd_by_adev(prange, adev);
    	if (pdd)
    		WRITE_ONCE(pdd->page_out, pdd->page_out + cpages);
- 
- 		return upages;
    }
    return r ? r : upages;
  }
@@@ -722,7 -734,7 +734,7 @@@
   * @prange: range structure
   * @mm: process mm, use current->mm if NULL
   *
-  * Context: Process context, caller hold mmap read lock, svms lock, prange lock
+  * Context: Process context, caller hold mmap read lock, prange->migrate_mutex
   *
   * Return:
   * 0 - OK, otherwise error code
@@@ -761,13 -773,16 +773,16 @@@ int svm_migrate_vram_to_ram(struct svm_
    	unsigned long next;
vma = find_vma(mm, addr);
- 		if (!vma || addr < vma->vm_start)
+ 		if (!vma || addr < vma->vm_start) {
+ 			pr_debug("failed to find vma for prange %p\n", prange);
+ 			r = -EFAULT;
    		break;
+ 		}
next = min(vma->vm_end, end);
    	r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next);
    	if (r < 0) {
- 			pr_debug("failed %ld to migrate\n", r);
+ 			pr_debug("failed %ld to migrate prange %p\n", r, prange);
    		break;
    	} else {
    		upages += r;
@@@ -775,7 -790,7 +790,7 @@@
    	addr = next;
    }
- 	if (!upages) {
+ 	if (r >= 0 && !upages) {
    	svm_range_vram_node_free(prange);
    	prange->actual_loc = 0;
    }
diff --combined drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 6d643b4b791d,f36062be9ca8..9967a73d5b0f
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@@ -1,5 -1,6 +1,6 @@@
+ /* SPDX-License-Identifier: GPL-2.0 OR MIT */
  /*
-  * Copyright 2014 Advanced Micro Devices, Inc.
+  * Copyright 2014-2022 Advanced Micro Devices, Inc.
   *
   * Permission is hereby granted, free of charge, to any person obtaining a
   * copy of this software and associated documentation files (the "Software"),
@@@ -25,7 -26,6 +26,7 @@@
#include <linux/hashtable.h>
  #include <linux/mmu_notifier.h>
 +#include <linux/memremap.h>
  #include <linux/mutex.h>
  #include <linux/types.h>
  #include <linux/atomic.h>
@@@ -122,7 -122,26 +123,26 @@@
   */
  #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
- 
+ /**
+  * enum kfd_ioctl_flags - KFD ioctl flags
+  * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how
+  * userspace can use a given ioctl.
+  */
+ enum kfd_ioctl_flags {
+ 	/*
+ 	 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE:
+ 	 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially
+ 	 * perform privileged operations and load arbitrary data into MQDs and
+ 	 * eventually HQD registers when the queue is mapped by HWS. In order to
+ 	 * prevent this we should perform additional security checks.
+ 	 *
+ 	 * This is equivalent to callers with the CHECKPOINT_RESTORE capability.
+ 	 *
+ 	 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE,
+ 	 * we also allow ioctls with SYS_ADMIN capability.
+ 	 */
+ 	KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
+ };
  /*
   * Kernel module parameter to specify maximum number of supported queues per
   * device
@@@ -282,9 -301,6 +302,6 @@@ struct kfd_dev 
     */
    bool interrupts_active;
- 	/* Debug manager */
- 	struct kfd_dbgmgr *dbgmgr;
- 
    /* Firmware versions */
    uint16_t mec_fw_version;
    uint16_t mec2_fw_version;
@@@ -339,25 -355,24 +356,24 @@@ enum kfd_mempool 
  /* Character device interface */
  int kfd_chardev_init(void);
  void kfd_chardev_exit(void);
- struct device *kfd_chardev(void);
/**
   * enum kfd_unmap_queues_filter - Enum for queue filters.
   *
-  * @KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE: Preempts single queue.
-  *
   * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
   *						running queues list.
   *
+  * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues
+  *						in the run list.
+  *
   * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
   *						specific process.
   *
   */
  enum kfd_unmap_queues_filter {
- 	KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE,
- 	KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
- 	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
- 	KFD_UNMAP_QUEUES_FILTER_BY_PASID
+ 	KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1,
+ 	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2,
+ 	KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3
  };
/**
@@@ -443,6 -458,7 +459,7 @@@ enum KFD_QUEUE_PRIORITY 
   * it's user mode or kernel mode queue.
   *
   */
+ 
  struct queue_properties {
    enum kfd_queue_type type;
    enum kfd_queue_format format;
@@@ -755,6 -771,12 +772,12 @@@ struct kfd_process_device 
    uint64_t faults;
    uint64_t page_in;
    uint64_t page_out;
+ 	/*
+ 	 * If this process has been checkpointed before, then the user
+ 	 * application will use the original gpu_id on the
+ 	 * checkpointed node to refer to this device.
+ 	 */
+ 	uint32_t user_gpu_id;
  };
#define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
@@@ -765,12 -787,13 +788,13 @@@ struct svm_range_list 
    struct list_head		list;
    struct work_struct		deferred_list_work;
    struct list_head		deferred_range_list;
+ 	struct list_head                criu_svm_metadata_list;
    spinlock_t			deferred_list_lock;
    atomic_t			evicted_ranges;
    atomic_t			drain_pagefaults;
    struct delayed_work		restore_work;
    DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
- 	struct task_struct 		*faulting_task;
+ 	struct task_struct		*faulting_task;
  };
/* Process data */
@@@ -859,6 -882,8 +883,8 @@@ struct kfd_process 
    bool xnack_enabled;
atomic_t poison;
+ 	/* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
+ 	bool queues_paused;
  };
#define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */
@@@ -889,7 -914,7 +915,7 @@@ bool kfd_dev_is_large_bar(struct kfd_de
  int kfd_process_create_wq(void);
  void kfd_process_destroy_wq(void);
  struct kfd_process *kfd_create_process(struct file *filep);
- struct kfd_process *kfd_get_process(const struct task_struct *);
+ struct kfd_process *kfd_get_process(const struct task_struct *task);
  struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);
  struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
@@@ -912,6 -937,11 +938,11 @@@ int kfd_process_restore_queues(struct k
  void kfd_suspend_all_processes(void);
  int kfd_resume_all_processes(void);
+ struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process,
+ 							 uint32_t gpu_id);
+ 
+ int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);
+ 
  int kfd_process_device_init_vm(struct kfd_process_device *pdd,
    		       struct file *drm_file);
  struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
@@@ -933,6 -963,7 +964,7 @@@ void *kfd_process_device_translate_hand
    				int handle);
  void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
    				int handle);
+ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);
/* PASIDs */
  int kfd_pasid_init(void);
@@@ -1007,6 -1038,116 +1039,116 @@@ void kfd_process_set_trap_handler(struc
    			  uint64_t tba_addr,
    			  uint64_t tma_addr);
+ /* CRIU */
+ /*
+  * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private
+  * structures:
+  * kfd_criu_process_priv_data
+  * kfd_criu_device_priv_data
+  * kfd_criu_bo_priv_data
+  * kfd_criu_queue_priv_data
+  * kfd_criu_event_priv_data
+  * kfd_criu_svm_range_priv_data
+  */
+ 
+ #define KFD_CRIU_PRIV_VERSION 1
+ 
+ struct kfd_criu_process_priv_data {
+ 	uint32_t version;
+ 	uint32_t xnack_mode;
+ };
+ 
+ struct kfd_criu_device_priv_data {
+ 	/* For future use */
+ 	uint64_t reserved;
+ };
+ 
+ struct kfd_criu_bo_priv_data {
+ 	uint64_t user_addr;
+ 	uint32_t idr_handle;
+ 	uint32_t mapped_gpuids[MAX_GPU_INSTANCE];
+ };
+ 
+ /*
+  * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data,
+  * kfd_criu_svm_range_priv_data is the object type
+  */
+ enum kfd_criu_object_type {
+ 	KFD_CRIU_OBJECT_TYPE_QUEUE,
+ 	KFD_CRIU_OBJECT_TYPE_EVENT,
+ 	KFD_CRIU_OBJECT_TYPE_SVM_RANGE,
+ };
+ 
+ struct kfd_criu_svm_range_priv_data {
+ 	uint32_t object_type;
+ 	uint64_t start_addr;
+ 	uint64_t size;
+ 	/* Variable length array of attributes */
+ 	struct kfd_ioctl_svm_attribute attrs[];
+ };
+ 
+ struct kfd_criu_queue_priv_data {
+ 	uint32_t object_type;
+ 	uint64_t q_address;
+ 	uint64_t q_size;
+ 	uint64_t read_ptr_addr;
+ 	uint64_t write_ptr_addr;
+ 	uint64_t doorbell_off;
+ 	uint64_t eop_ring_buffer_address;
+ 	uint64_t ctx_save_restore_area_address;
+ 	uint32_t gpu_id;
+ 	uint32_t type;
+ 	uint32_t format;
+ 	uint32_t q_id;
+ 	uint32_t priority;
+ 	uint32_t q_percent;
+ 	uint32_t doorbell_id;
+ 	uint32_t is_gws;
+ 	uint32_t sdma_id;
+ 	uint32_t eop_ring_buffer_size;
+ 	uint32_t ctx_save_restore_area_size;
+ 	uint32_t ctl_stack_size;
+ 	uint32_t mqd_size;
+ };
+ 
+ struct kfd_criu_event_priv_data {
+ 	uint32_t object_type;
+ 	uint64_t user_handle;
+ 	uint32_t event_id;
+ 	uint32_t auto_reset;
+ 	uint32_t type;
+ 	uint32_t signaled;
+ 
+ 	union {
+ 		struct kfd_hsa_memory_exception_data memory_exception_data;
+ 		struct kfd_hsa_hw_exception_data hw_exception_data;
+ 	};
+ };
+ 
+ int kfd_process_get_queue_info(struct kfd_process *p,
+ 			       uint32_t *num_queues,
+ 			       uint64_t *priv_data_sizes);
+ 
+ int kfd_criu_checkpoint_queues(struct kfd_process *p,
+ 			 uint8_t __user *user_priv_data,
+ 			 uint64_t *priv_data_offset);
+ 
+ int kfd_criu_restore_queue(struct kfd_process *p,
+ 			   uint8_t __user *user_priv_data,
+ 			   uint64_t *priv_data_offset,
+ 			   uint64_t max_priv_data_size);
+ 
+ int kfd_criu_checkpoint_events(struct kfd_process *p,
+ 			 uint8_t __user *user_priv_data,
+ 			 uint64_t *priv_data_offset);
+ 
+ int kfd_criu_restore_event(struct file *devkfd,
+ 			   struct kfd_process *p,
+ 			   uint8_t __user *user_priv_data,
+ 			   uint64_t *priv_data_offset,
+ 			   uint64_t max_priv_data_size);
+ /* CRIU - End */
+ 
  /* Queue Context Management */
  int init_queue(struct queue **q, const struct queue_properties *properties);
  void uninit_queue(struct queue *q);
@@@ -1030,7 -1171,7 +1172,7 @@@ void device_queue_manager_uninit(struc
  struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
    				enum kfd_queue_type type);
  void kernel_queue_uninit(struct kernel_queue *kq, bool hanging);
- int kfd_process_vm_fault(struct device_queue_manager *dqm, u32 pasid);
+ int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid);
/* Process Queue Manager */
  struct process_queue_node {
@@@ -1048,6 -1189,9 +1190,9 @@@ int pqm_create_queue(struct process_que
    		    struct file *f,
    		    struct queue_properties *properties,
    		    unsigned int *qid,
+ 			    const struct kfd_criu_queue_priv_data *q_data,
+ 			    const void *restore_mqd,
+ 			    const void *restore_ctl_stack,
    		    uint32_t *p_doorbell_offset_in_process);
  int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
  int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid,
@@@ -1070,6 -1214,10 +1215,10 @@@ int amdkfd_fence_wait_timeout(uint64_t 
    		      uint64_t fence_value,
    		      unsigned int timeout_ms);
+ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
+ 				  unsigned int qid,
+ 				  u32 *mqd_size,
+ 				  u32 *ctl_stack_size);
  /* Packet Manager */
#define KFD_FENCE_COMPLETED (100)
@@@ -1098,10 -1246,8 +1247,8 @@@ struct packet_manager_funcs 
    int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,
    		struct queue *q, bool is_static);
    int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,
- 			enum kfd_queue_type type,
    		enum kfd_unmap_queues_filter mode,
- 			uint32_t filter_param, bool reset,
- 			unsigned int sdma_engine);
+ 			uint32_t filter_param, bool reset);
    int (*query_status)(struct packet_manager *pm, uint32_t *buffer,
    		uint64_t fence_address,	uint64_t fence_value);
    int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);
@@@ -1128,10 -1274,9 +1275,9 @@@ int pm_send_runlist(struct packet_manag
  int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
    			uint64_t fence_value);
- int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
+ int pm_send_unmap_queue(struct packet_manager *pm,
    		enum kfd_unmap_queues_filter mode,
- 			uint32_t filter_param, bool reset,
- 			unsigned int sdma_engine);
+ 			uint32_t filter_param, bool reset);
void pm_release_ib(struct packet_manager *pm);
@@@ -1161,12 -1306,14 +1307,14 @@@ void kfd_signal_iommu_event(struct kfd_
  void kfd_signal_hw_exception_event(u32 pasid);
  int kfd_set_event(struct kfd_process *p, uint32_t event_id);
  int kfd_reset_event(struct kfd_process *p, uint32_t event_id);
- int kfd_event_page_set(struct kfd_process *p, void *kernel_address,
- 		       uint64_t size);
+ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset);
+ 
  int kfd_event_create(struct file *devkfd, struct kfd_process *p,
    	     uint32_t event_type, bool auto_reset, uint32_t node_id,
    	     uint32_t *event_id, uint32_t *event_trigger_data,
    	     uint64_t *event_page_offset, uint32_t *event_slot_index);
+ 
+ int kfd_get_num_events(struct kfd_process *p);
  int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);
void kfd_signal_vm_fault_event(struct kfd_dev *dev, u32 pasid,
@@@ -1178,8 -1325,6 +1326,6 @@@ void kfd_signal_poison_consumed_event(s
void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);
- int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p);
- 
  bool kfd_is_locked(void);
/* Compute profile */
diff --combined drivers/gpu/drm/bridge/Kconfig
index 44ad70939663,c86f5be4dfe0..007e5a282f67
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@@ -8,6 -8,7 +8,6 @@@ config DRM_BRIDG
  config DRM_PANEL_BRIDGE
    def_bool y
    depends on DRM_BRIDGE
 -	depends on DRM_KMS_HELPER
    select DRM_PANEL
    help
      DRM bridge wrapper of DRM panels
@@@ -29,7 -30,7 +29,7 @@@ config DRM_CDNS_DS
  config DRM_CHIPONE_ICN6211
    tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
    depends on OF
 -	depends on DRM_KMS_HELPER
 +	select DRM_KMS_HELPER
    select DRM_MIPI_DSI
    select DRM_PANEL_BRIDGE
    help
@@@ -74,6 -75,14 +74,14 @@@ config DRM_DISPLAY_CONNECTO
      on ARM-based platforms. Saying Y here when this driver is not needed
      will not cause any issue.
+ config DRM_ITE_IT6505
+         tristate "ITE IT6505 DisplayPort bridge"
+         depends on OF
+         select DRM_KMS_HELPER
+         select EXTCON
+         help
+           ITE IT6505 DisplayPort bridge chip driver.
+ 
  config DRM_LONTIUM_LT8912B
    tristate "Lontium LT8912B DSI/HDMI bridge"
    depends on OF
@@@ -183,6 -192,7 +191,7 @@@ config DRM_PARADE_PS864
    tristate "Parade PS8640 MIPI DSI to eDP Converter"
    depends on OF
    select DRM_DP_AUX_BUS
+ 	select DRM_DP_HELPER
    select DRM_KMS_HELPER
    select DRM_MIPI_DSI
    select DRM_PANEL
@@@ -253,6 -263,7 +262,7 @@@ config DRM_TOSHIBA_TC35876
  config DRM_TOSHIBA_TC358767
    tristate "Toshiba TC358767 eDP bridge"
    depends on OF
+ 	select DRM_DP_HELPER
    select DRM_KMS_HELPER
    select REGMAP_I2C
    select DRM_PANEL
@@@ -272,6 -283,7 +282,7 @@@ config DRM_TOSHIBA_TC35876
  config DRM_TOSHIBA_TC358775
    tristate "Toshiba TC358775 DSI/LVDS bridge"
    depends on OF
+ 	select DRM_DP_HELPER
    select DRM_KMS_HELPER
    select REGMAP_I2C
    select DRM_PANEL
@@@ -299,6 -311,7 +310,7 @@@ config DRM_TI_SN65DSI8
  config DRM_TI_SN65DSI86
    tristate "TI SN65DSI86 DSI to eDP bridge"
    depends on OF
+ 	select DRM_DP_HELPER
    select DRM_KMS_HELPER
    select REGMAP_I2C
    select DRM_PANEL
diff --combined drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 68d8415e6c28,38616aab12ac..fb6c588b0f71
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@@ -26,8 -26,9 +26,9 @@@
  #include <drm/drm_atomic.h>
  #include <drm/drm_atomic_helper.h>
  #include <drm/drm_bridge.h>
- #include <drm/drm_dp_aux_bus.h>
- #include <drm/drm_dp_helper.h>
+ #include <drm/drm_bridge_connector.h>
+ #include <drm/dp/drm_dp_aux_bus.h>
+ #include <drm/dp/drm_dp_helper.h>
  #include <drm/drm_mipi_dsi.h>
  #include <drm/drm_of.h>
  #include <drm/drm_panel.h>
@@@ -174,7 -175,7 +175,7 @@@ struct ti_sn65dsi86 
    struct regmap			*regmap;
    struct drm_dp_aux		aux;
    struct drm_bridge		bridge;
- 	struct drm_connector		connector;
+ 	struct drm_connector		*connector;
    struct device_node		*host_node;
    struct mipi_dsi_device		*dsi;
    struct clk			*refclk;
@@@ -646,54 -647,6 +647,6 @@@ static struct auxiliary_driver ti_sn_au
    .id_table = ti_sn_aux_id_table,
  };
- /* -----------------------------------------------------------------------------
-  * DRM Connector Operations
-  */
- 
- static struct ti_sn65dsi86 *
- connector_to_ti_sn65dsi86(struct drm_connector *connector)
- {
- 	return container_of(connector, struct ti_sn65dsi86, connector);
- }
- 
- static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
- {
- 	struct ti_sn65dsi86 *pdata = connector_to_ti_sn65dsi86(connector);
- 
- 	return drm_bridge_get_modes(pdata->next_bridge, connector);
- }
- 
- static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
- 	.get_modes = ti_sn_bridge_connector_get_modes,
- };
- 
- static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
- 	.fill_modes = drm_helper_probe_single_connector_modes,
- 	.destroy = drm_connector_cleanup,
- 	.reset = drm_atomic_helper_connector_reset,
- 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
- };
- 
- static int ti_sn_bridge_connector_init(struct ti_sn65dsi86 *pdata)
- {
- 	int ret;
- 
- 	ret = drm_connector_init(pdata->bridge.dev, &pdata->connector,
- 				 &ti_sn_bridge_connector_funcs,
- 				 DRM_MODE_CONNECTOR_eDP);
- 	if (ret) {
- 		DRM_ERROR("Failed to initialize connector with drm\n");
- 		return ret;
- 	}
- 
- 	drm_connector_helper_add(&pdata->connector,
- 				 &ti_sn_bridge_connector_helper_funcs);
- 	drm_connector_attach_encoder(&pdata->connector, pdata->bridge.encoder);
- 
- 	return 0;
- }
- 
  /*------------------------------------------------------------------------------
   * DRM Bridge
   */
@@@ -757,10 -710,6 +710,6 @@@ static int ti_sn_bridge_attach(struct d
    	return ret;
    }
- 	ret = ti_sn_bridge_connector_init(pdata);
- 	if (ret < 0)
- 		goto err_conn_init;
- 
    /* We never want the next bridge to *also* create a connector: */
    flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
@@@ -768,13 -717,20 +717,20 @@@
    ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
    			&pdata->bridge, flags);
    if (ret < 0)
- 		goto err_dsi_host;
+ 		goto err_initted_aux;
+ 
+ 	pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
+ 						     pdata->bridge.encoder);
+ 	if (IS_ERR(pdata->connector)) {
+ 		ret = PTR_ERR(pdata->connector);
+ 		goto err_initted_aux;
+ 	}
+ 
+ 	drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
return 0;
- err_dsi_host:
- 	drm_connector_cleanup(&pdata->connector);
- err_conn_init:
+ err_initted_aux:
    drm_dp_aux_unregister(&pdata->aux);
    return ret;
  }
@@@ -824,7 -780,7 +780,7 @@@ static void ti_sn_bridge_set_dsi_rate(s
static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
  {
- 	if (pdata->connector.display_info.bpc <= 6)
+ 	if (pdata->connector->display_info.bpc <= 6)
    	return 18;
    else
    	return 24;
@@@ -1802,7 -1758,6 +1758,7 @@@ static inline void ti_sn_gpio_unregiste
static void ti_sn65dsi86_runtime_disable(void *data)
  {
 +	pm_runtime_dont_use_autosuspend(data);
    pm_runtime_disable(data);
  }
@@@ -1862,11 -1817,11 +1818,11 @@@ static int ti_sn65dsi86_probe(struct i2
    			     "failed to get reference clock\n");
pm_runtime_enable(dev);
 +	pm_runtime_set_autosuspend_delay(pdata->dev, 500);
 +	pm_runtime_use_autosuspend(pdata->dev);
    ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
    if (ret)
    	return ret;
 -	pm_runtime_set_autosuspend_delay(pdata->dev, 500);
 -	pm_runtime_use_autosuspend(pdata->dev);
ti_sn65dsi86_debugfs_init(pdata);
diff --combined drivers/gpu/drm/drm_cache.c
index 50b8a088f763,c3e6e615bf09..7051c9c909c2
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@@ -27,11 -27,11 +27,11 @@@
  /*
   * Authors: Thomas Hellstr��m <thomas-at-tungstengraphics-dot-com>
   */
- #include <linux/dma-buf-map.h>
 -
+ #include <linux/cc_platform.h>
  #include <linux/export.h>
  #include <linux/highmem.h>
- #include <linux/cc_platform.h>
 +#include <linux/ioport.h>
+ #include <linux/iosys-map.h>
  #include <xen/xen.h>
#include <drm/drm_cache.h>
@@@ -112,8 -112,7 +112,7 @@@ drm_clflush_pages(struct page *pages[]
    	kunmap_atomic(page_virtual);
    }
  #else
- 	pr_err("Architecture has no drm_cache.c support\n");
- 	WARN_ON_ONCE(1);
+ 	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
  #endif
  }
  EXPORT_SYMBOL(drm_clflush_pages);
@@@ -143,8 -142,7 +142,7 @@@ drm_clflush_sg(struct sg_table *st
    if (wbinvd_on_all_cpus())
    	pr_err("Timed out waiting for cache flush\n");
  #else
- 	pr_err("Architecture has no drm_cache.c support\n");
- 	WARN_ON_ONCE(1);
+ 	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
  #endif
  }
  EXPORT_SYMBOL(drm_clflush_sg);
@@@ -177,8 -175,7 +175,7 @@@ drm_clflush_virt_range(void *addr, unsi
    if (wbinvd_on_all_cpus())
    	pr_err("Timed out waiting for cache flush\n");
  #else
- 	pr_err("Architecture has no drm_cache.c support\n");
- 	WARN_ON_ONCE(1);
+ 	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
  #endif
  }
  EXPORT_SYMBOL(drm_clflush_virt_range);
@@@ -214,14 -211,14 +211,14 @@@ bool drm_need_swiotlb(int dma_bits
  }
  EXPORT_SYMBOL(drm_need_swiotlb);
- static void memcpy_fallback(struct dma_buf_map *dst,
- 			    const struct dma_buf_map *src,
+ static void memcpy_fallback(struct iosys_map *dst,
+ 			    const struct iosys_map *src,
    		    unsigned long len)
  {
    if (!dst->is_iomem && !src->is_iomem) {
    	memcpy(dst->vaddr, src->vaddr, len);
    } else if (!src->is_iomem) {
- 		dma_buf_map_memcpy_to(dst, src->vaddr, len);
+ 		iosys_map_memcpy_to(dst, 0, src->vaddr, len);
    } else if (!dst->is_iomem) {
    	memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
    } else {
@@@ -305,8 -302,8 +302,8 @@@ static void __drm_memcpy_from_wc(void *
   * Tries an arch optimized memcpy for prefetching reading out of a WC region,
   * and if no such beast is available, falls back to a normal memcpy.
   */
- void drm_memcpy_from_wc(struct dma_buf_map *dst,
- 			const struct dma_buf_map *src,
+ void drm_memcpy_from_wc(struct iosys_map *dst,
+ 			const struct iosys_map *src,
    		unsigned long len)
  {
    if (WARN_ON(in_interrupt())) {
@@@ -343,8 -340,8 +340,8 @@@ void drm_memcpy_init_early(void
    	static_branch_enable(&has_movntdqa);
  }
  #else
- void drm_memcpy_from_wc(struct dma_buf_map *dst,
- 			const struct dma_buf_map *src,
+ void drm_memcpy_from_wc(struct iosys_map *dst,
+ 			const struct iosys_map *src,
    		unsigned long len)
  {
    WARN_ON(in_interrupt());
diff --combined drivers/gpu/drm/i915/display/intel_psr.c
index 00279e8c2775,5895b89df03a..bff8c2d73cdf
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@@ -1063,31 -1063,28 +1063,28 @@@ static void intel_psr_activate(struct i
    intel_dp->psr.active = true;
  }
- static void intel_psr_enable_source(struct intel_dp *intel_dp)
+ static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
+ {
+ 	switch (intel_dp->psr.pipe) {
+ 	case PIPE_A:
+ 		return LATENCY_REPORTING_REMOVED_PIPE_A;
+ 	case PIPE_B:
+ 		return LATENCY_REPORTING_REMOVED_PIPE_B;
+ 	case PIPE_C:
+ 		return LATENCY_REPORTING_REMOVED_PIPE_C;
+ 	default:
+ 		MISSING_CASE(intel_dp->psr.pipe);
+ 		return 0;
+ 	}
+ }
+ 
+ static void intel_psr_enable_source(struct intel_dp *intel_dp,
+ 				    const struct intel_crtc_state *crtc_state)
  {
    struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
    enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
    u32 mask;
- 	if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
- 		i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
- 		u32 chicken = intel_de_read(dev_priv, reg);
- 
- 		chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
- 			   PSR2_ADD_VERTICAL_LINE_COUNT;
- 		intel_de_write(dev_priv, reg, chicken);
- 	}
- 
- 	/*
- 	 * Wa_16014451276:adlp
- 	 * All supported adlp panels have 1-based X granularity, this may
- 	 * cause issues if non-supported panels are used.
- 	 */
- 	if (IS_ALDERLAKE_P(dev_priv) &&
- 	    intel_dp->psr.psr2_enabled)
- 		intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
- 			     ADLP_1_BASED_X_GRANULARITY);
- 
    /*
     * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
     * mask LPSP to avoid dependency on other drivers that might block
@@@ -1126,18 -1123,47 +1123,47 @@@
    		     intel_dp->psr.psr2_sel_fetch_enabled ?
    		     IGNORE_PSR2_HW_TRACKING : 0);
- 	/* Wa_16011168373:adl-p */
- 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
- 	    intel_dp->psr.psr2_enabled)
- 		intel_de_rmw(dev_priv,
- 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
- 			     TRANS_SET_CONTEXT_LATENCY_MASK,
- 			     TRANS_SET_CONTEXT_LATENCY_VALUE(1));
- 
- 	/* Wa_16012604467:adlp */
- 	if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
- 		intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
- 			     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
+ 	if (intel_dp->psr.psr2_enabled) {
+ 		if (DISPLAY_VER(dev_priv) == 9)
+ 			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ 				     PSR2_VSC_ENABLE_PROG_HEADER |
+ 				     PSR2_ADD_VERTICAL_LINE_COUNT);
+ 
+ 		/*
+ 		 * Wa_16014451276:adlp
+ 		 * All supported adlp panels have 1-based X granularity, this may
+ 		 * cause issues if non-supported panels are used.
+ 		 */
+ 		if (IS_ALDERLAKE_P(dev_priv))
+ 			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ 				     ADLP_1_BASED_X_GRANULARITY);
+ 
+ 		/* Wa_16011168373:adl-p */
+ 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ 			intel_de_rmw(dev_priv,
+ 				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
+ 				     TRANS_SET_CONTEXT_LATENCY_MASK,
+ 				     TRANS_SET_CONTEXT_LATENCY_VALUE(1));
+ 
+ 		/* Wa_16012604467:adlp */
+ 		if (IS_ALDERLAKE_P(dev_priv))
+ 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
+ 				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
+ 
+ 		/* Wa_16013835468:tgl[b0+], dg1 */
+ 		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
+ 		    IS_DG1(dev_priv)) {
+ 			u16 vtotal, vblank;
+ 
+ 			vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
+ 				 crtc_state->uapi.adjusted_mode.crtc_vdisplay;
+ 			vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
+ 				 crtc_state->uapi.adjusted_mode.crtc_vblank_start;
+ 			if (vblank > vtotal)
+ 				intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
+ 					     wa_16013835468_bit_get(intel_dp));
+ 		}
+ 	}
  }
static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
@@@ -1202,7 -1228,7 +1228,7 @@@ static void intel_psr_enable_locked(str
    intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
    intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
    intel_psr_enable_sink(intel_dp);
- 	intel_psr_enable_source(intel_dp);
+ 	intel_psr_enable_source(intel_dp, crtc_state);
    intel_dp->psr.enabled = true;
    intel_dp->psr.paused = false;
@@@ -1290,17 -1316,24 +1316,24 @@@ static void intel_psr_disable_locked(st
    	intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
    		     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
- 	/* Wa_16011168373:adl-p */
- 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
- 	    intel_dp->psr.psr2_enabled)
- 		intel_de_rmw(dev_priv,
- 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
- 			     TRANS_SET_CONTEXT_LATENCY_MASK, 0);
- 
- 	/* Wa_16012604467:adlp */
- 	if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)
- 		intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
- 			     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
+ 	if (intel_dp->psr.psr2_enabled) {
+ 		/* Wa_16011168373:adl-p */
+ 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ 			intel_de_rmw(dev_priv,
+ 				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
+ 				     TRANS_SET_CONTEXT_LATENCY_MASK, 0);
+ 
+ 		/* Wa_16012604467:adlp */
+ 		if (IS_ALDERLAKE_P(dev_priv))
+ 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
+ 				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
+ 
+ 		/* Wa_16013835468:tgl[b0+], dg1 */
+ 		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
+ 		    IS_DG1(dev_priv))
+ 			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ 				     wa_16013835468_bit_get(intel_dp), 0);
+ 	}
intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
@@@ -1406,13 -1439,6 +1439,13 @@@ static inline u32 man_trk_ctl_single_fu
           PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
  }
+static inline u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
 +{
 +	return IS_ALDERLAKE_P(dev_priv) ?
 +	       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
 +	       PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
 +}
 +
  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
  {
    struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@@ -1517,13 -1543,7 +1550,13 @@@ static void psr2_man_trk_ctl_calc(struc
  {
    struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
    struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 -	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
 +	u32 val = 0;
 +
 +	if (!IS_ALDERLAKE_P(dev_priv))
 +		val = PSR2_MAN_TRK_CTL_ENABLE;
 +
 +	/* SF partial frame enable has to be set even on full update */
 +	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
if (full_update) {
    	/*
@@@ -1543,6 -1563,7 +1576,6 @@@
    } else {
    	drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
-		val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
    	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
    	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
    }
@@@ -1816,6 -1837,9 +1849,9 @@@ static void _intel_psr_post_plane_updat
mutex_lock(&psr->lock);
+ 		if (psr->sink_not_reliable)
+ 			goto exit;
+ 
    	drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
/* Only enable if there is active planes */
@@@ -1826,6 -1850,7 +1862,7 @@@
    	if (crtc_state->crc_enabled && psr->enabled)
    		psr_force_hw_tracking_exit(intel_dp);
+ exit:
    	mutex_unlock(&psr->lock);
    }
  }
diff --combined drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 3acee0060e23,9bb551b83e7a..92cb88248391
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@@ -5,7 -5,9 +5,9 @@@
#include <linux/bsearch.h>
+ #include "gt/intel_engine_regs.h"
  #include "gt/intel_gt.h"
+ #include "gt/intel_gt_regs.h"
  #include "gt/intel_lrc.h"
  #include "gt/shmem_utils.h"
  #include "intel_guc_ads.h"
@@@ -40,6 -42,10 +42,10 @@@
   *      +---------------------------------------+
   *      | padding                               |
   *      +---------------------------------------+ <== 4K aligned
+  *      | capture lists                         |
+  *      +---------------------------------------+
+  *      | padding                               |
+  *      +---------------------------------------+ <== 4K aligned
   *      | private data                          |
   *      +---------------------------------------+
   *      | padding                               |
@@@ -51,9 -57,22 +57,22 @@@ struct __guc_ads_blob 
    struct guc_gt_system_info system_info;
    struct guc_engine_usage engine_usage;
    /* From here on, location is dynamic! Refer to above diagram. */
 -	struct guc_mmio_reg regset[0];
 +	struct guc_mmio_reg regset[];
  } __packed;
+ #define ads_blob_read(guc_, field_)					\
+ 	iosys_map_rd_field(&(guc_)->ads_map, 0, struct __guc_ads_blob, field_)
+ 
+ #define ads_blob_write(guc_, field_, val_)				\
+ 	iosys_map_wr_field(&(guc_)->ads_map, 0, struct __guc_ads_blob,	\
+ 			   field_, val_)
+ 
+ #define info_map_write(map_, field_, val_) \
+ 	iosys_map_wr_field(map_, 0, struct guc_gt_system_info, field_, val_)
+ 
+ #define info_map_read(map_, field_) \
+ 	iosys_map_rd_field(map_, 0, struct guc_gt_system_info, field_)
+ 
  static u32 guc_ads_regset_size(struct intel_guc *guc)
  {
    GEM_BUG_ON(!guc->ads_regset_size);
@@@ -65,6 -84,12 +84,12 @@@ static u32 guc_ads_golden_ctxt_size(str
    return PAGE_ALIGN(guc->ads_golden_ctxt_size);
  }
+ static u32 guc_ads_capture_size(struct intel_guc *guc)
+ {
+ 	/* FIXME: Allocate a proper capture list */
+ 	return PAGE_ALIGN(PAGE_SIZE);
+ }
+ 
  static u32 guc_ads_private_data_size(struct intel_guc *guc)
  {
    return PAGE_ALIGN(guc->fw.private_data_size);
@@@ -85,7 -110,7 +110,7 @@@ static u32 guc_ads_golden_ctxt_offset(s
    return PAGE_ALIGN(offset);
  }
- static u32 guc_ads_private_data_offset(struct intel_guc *guc)
+ static u32 guc_ads_capture_offset(struct intel_guc *guc)
  {
    u32 offset;
@@@ -95,39 -120,53 +120,53 @@@
    return PAGE_ALIGN(offset);
  }
+ static u32 guc_ads_private_data_offset(struct intel_guc *guc)
+ {
+ 	u32 offset;
+ 
+ 	offset = guc_ads_capture_offset(guc) +
+ 		 guc_ads_capture_size(guc);
+ 
+ 	return PAGE_ALIGN(offset);
+ }
+ 
  static u32 guc_ads_blob_size(struct intel_guc *guc)
  {
    return guc_ads_private_data_offset(guc) +
           guc_ads_private_data_size(guc);
  }
- static void guc_policies_init(struct intel_guc *guc, struct guc_policies *policies)
+ static void guc_policies_init(struct intel_guc *guc)
  {
    struct intel_gt *gt = guc_to_gt(guc);
    struct drm_i915_private *i915 = gt->i915;
+ 	u32 global_flags = 0;
- 	policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
- 	policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;
+ 	ads_blob_write(guc, policies.dpc_promote_time,
+ 		       GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);
+ 	ads_blob_write(guc, policies.max_num_work_items,
+ 		       GLOBAL_POLICY_MAX_NUM_WI);
- 	policies->global_flags = 0;
    if (i915->params.reset < 2)
- 		policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
+ 		global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
- 	policies->is_valid = 1;
+ 	ads_blob_write(guc, policies.global_flags, global_flags);
+ 	ads_blob_write(guc, policies.is_valid, 1);
  }
void intel_guc_ads_print_policy_info(struct intel_guc *guc,
    			     struct drm_printer *dp)
  {
- 	struct __guc_ads_blob *blob = guc->ads_blob;
- 
- 	if (unlikely(!blob))
+ 	if (unlikely(iosys_map_is_null(&guc->ads_map)))
    	return;
drm_printf(dp, "Global scheduling policies:\n");
- 	drm_printf(dp, "  DPC promote time   = %u\n", blob->policies.dpc_promote_time);
- 	drm_printf(dp, "  Max num work items = %u\n", blob->policies.max_num_work_items);
- 	drm_printf(dp, "  Flags              = %u\n", blob->policies.global_flags);
+ 	drm_printf(dp, "  DPC promote time   = %u\n",
+ 		   ads_blob_read(guc, policies.dpc_promote_time));
+ 	drm_printf(dp, "  Max num work items = %u\n",
+ 		   ads_blob_read(guc, policies.max_num_work_items));
+ 	drm_printf(dp, "  Flags              = %u\n",
+ 		   ads_blob_read(guc, policies.global_flags));
  }
static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset)
@@@ -142,29 -181,30 +181,30 @@@
int intel_guc_global_policies_update(struct intel_guc *guc)
  {
- 	struct __guc_ads_blob *blob = guc->ads_blob;
    struct intel_gt *gt = guc_to_gt(guc);
+ 	u32 scheduler_policies;
    intel_wakeref_t wakeref;
    int ret;
- 	if (!blob)
+ 	if (iosys_map_is_null(&guc->ads_map))
    	return -EOPNOTSUPP;
- 	GEM_BUG_ON(!blob->ads.scheduler_policies);
+ 	scheduler_policies = ads_blob_read(guc, ads.scheduler_policies);
+ 	GEM_BUG_ON(!scheduler_policies);
- 	guc_policies_init(guc, &blob->policies);
+ 	guc_policies_init(guc);
if (!intel_guc_is_ready(guc))
    	return 0;
with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
- 		ret = guc_action_policies_update(guc, blob->ads.scheduler_policies);
+ 		ret = guc_action_policies_update(guc, scheduler_policies);
return ret;
  }
static void guc_mapping_table_init(struct intel_gt *gt,
- 				   struct guc_gt_system_info *system_info)
+ 				   struct iosys_map *info_map)
  {
    unsigned int i, j;
    struct intel_engine_cs *engine;
@@@ -173,27 -213,31 +213,31 @@@
    /* Table must be set to invalid values for entries not used */
    for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)
    	for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j)
- 			system_info->mapping_table[i][j] =
- 				GUC_MAX_INSTANCES_PER_CLASS;
+ 			info_map_write(info_map, mapping_table[i][j],
+ 				       GUC_MAX_INSTANCES_PER_CLASS);
for_each_engine(engine, gt, id) {
    	u8 guc_class = engine_class_to_guc_class(engine->class);
- 		system_info->mapping_table[guc_class][ilog2(engine->logical_mask)] =
- 			engine->instance;
+ 		info_map_write(info_map, mapping_table[guc_class][ilog2(engine->logical_mask)],
+ 			       engine->instance);
    }
  }
/*
   * The save/restore register list must be pre-calculated to a temporary
-  * buffer of driver defined size before it can be generated in place
-  * inside the ADS.
+  * buffer before it can be copied inside the ADS.
   */
- #define MAX_MMIO_REGS	128	/* Arbitrary size, increase as needed */
  struct temp_regset {
+ 	/*
+ 	 * ptr to the section of the storage for the engine currently being
+ 	 * worked on
+ 	 */
    struct guc_mmio_reg *registers;
- 	u32 used;
- 	u32 size;
+ 	/* ptr to the base of the allocated storage for all engines */
+ 	struct guc_mmio_reg *storage;
+ 	u32 storage_used;
+ 	u32 storage_max;
  };
static int guc_mmio_reg_cmp(const void *a, const void *b)
@@@ -204,18 -248,44 +248,44 @@@
    return (int)ra->offset - (int)rb->offset;
  }
- static void guc_mmio_reg_add(struct temp_regset *regset,
- 			     u32 offset, u32 flags)
+ static struct guc_mmio_reg * __must_check
+ __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
+ {
+ 	u32 pos = regset->storage_used;
+ 	struct guc_mmio_reg *slot;
+ 
+ 	if (pos >= regset->storage_max) {
+ 		size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE);
+ 		struct guc_mmio_reg *r = krealloc(regset->storage,
+ 						  size, GFP_KERNEL);
+ 		if (!r) {
+ 			WARN_ONCE(1, "Incomplete regset list: can't add register (%d)\n",
+ 				  -ENOMEM);
+ 			return ERR_PTR(-ENOMEM);
+ 		}
+ 
+ 		regset->registers = r + (regset->registers - regset->storage);
+ 		regset->storage = r;
+ 		regset->storage_max = size / sizeof(*slot);
+ 	}
+ 
+ 	slot = &regset->storage[pos];
+ 	regset->storage_used++;
+ 	*slot = *reg;
+ 
+ 	return slot;
+ }
+ 
+ static long __must_check guc_mmio_reg_add(struct temp_regset *regset,
+ 					  u32 offset, u32 flags)
  {
- 	u32 count = regset->used;
+ 	u32 count = regset->storage_used - (regset->registers - regset->storage);
    struct guc_mmio_reg reg = {
    	.offset = offset,
    	.flags = flags,
    };
    struct guc_mmio_reg *slot;
- 	GEM_BUG_ON(count >= regset->size);
- 
    /*
     * The mmio list is built using separate lists within the driver.
     * It's possible that at some point we may attempt to add the same
@@@ -224,11 -294,11 +294,11 @@@
     */
    if (bsearch(&reg, regset->registers, count,
    	    sizeof(reg), guc_mmio_reg_cmp))
- 		return;
+ 		return 0;
- 	slot = &regset->registers[count];
- 	regset->used++;
- 	*slot = reg;
+ 	slot = __mmio_reg_add(regset, &reg);
+ 	if (IS_ERR(slot))
+ 		return PTR_ERR(slot);
while (slot-- > regset->registers) {
    	GEM_BUG_ON(slot[0].offset == slot[1].offset);
@@@ -237,6 -307,8 +307,8 @@@
swap(slot[1], slot[0]);
    }
+ 
+ 	return 0;
  }
#define GUC_MMIO_REG_ADD(regset, reg, masked) \
@@@ -244,124 -316,140 +316,140 @@@
    		 i915_mmio_reg_offset((reg)), \
    		 (masked) ? GUC_REGSET_MASKED : 0)
- static void guc_mmio_regset_init(struct temp_regset *regset,
- 				 struct intel_engine_cs *engine)
+ static int guc_mmio_regset_init(struct temp_regset *regset,
+ 				struct intel_engine_cs *engine)
  {
    const u32 base = engine->mmio_base;
    struct i915_wa_list *wal = &engine->wa_list;
    struct i915_wa *wa;
    unsigned int i;
+ 	int ret = 0;
- 	regset->used = 0;
+ 	/*
+ 	 * Each engine's registers point to a new start relative to
+ 	 * storage
+ 	 */
+ 	regset->registers = regset->storage + regset->storage_used;
- 	GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
- 	GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
- 	GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
+ 	ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
+ 	ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
+ 	ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
+ 
+ 	if (engine->class == RENDER_CLASS &&
+ 	    CCS_MASK(engine->gt))
+ 		ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- 		GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
+ 		ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
/* Be extra paranoid and include all whitelist registers. */
    for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
- 		GUC_MMIO_REG_ADD(regset,
- 				 RING_FORCE_TO_NONPRIV(base, i),
- 				 false);
+ 		ret |= GUC_MMIO_REG_ADD(regset,
+ 					RING_FORCE_TO_NONPRIV(base, i),
+ 					false);
/* add in local MOCS registers */
    for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
- 		GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+ 		ret |= GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+ 
+ 	return ret ? -1 : 0;
  }
- static int guc_mmio_reg_state_query(struct intel_guc *guc)
+ static long guc_mmio_reg_state_create(struct intel_guc *guc)
  {
    struct intel_gt *gt = guc_to_gt(guc);
    struct intel_engine_cs *engine;
    enum intel_engine_id id;
- 	struct temp_regset temp_set;
- 	u32 total;
+ 	struct temp_regset temp_set = {};
+ 	long total = 0;
+ 	long ret;
- 	/*
- 	 * Need to actually build the list in order to filter out
- 	 * duplicates and other such data dependent constructions.
- 	 */
- 	temp_set.size = MAX_MMIO_REGS;
- 	temp_set.registers = kmalloc_array(temp_set.size,
- 					   sizeof(*temp_set.registers),
- 					   GFP_KERNEL);
- 	if (!temp_set.registers)
- 		return -ENOMEM;
- 
- 	total = 0;
    for_each_engine(engine, gt, id) {
- 		guc_mmio_regset_init(&temp_set, engine);
- 		total += temp_set.used;
+ 		u32 used = temp_set.storage_used;
+ 
+ 		ret = guc_mmio_regset_init(&temp_set, engine);
+ 		if (ret < 0)
+ 			goto fail_regset_init;
+ 
+ 		guc->ads_regset_count[id] = temp_set.storage_used - used;
+ 		total += guc->ads_regset_count[id];
    }
- 	kfree(temp_set.registers);
+ 	guc->ads_regset = temp_set.storage;
+ 
+ 	drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n",
+ 		(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
return total * sizeof(struct guc_mmio_reg);
+ 
+ fail_regset_init:
+ 	kfree(temp_set.storage);
+ 	return ret;
  }
- static void guc_mmio_reg_state_init(struct intel_guc *guc,
- 				    struct __guc_ads_blob *blob)
+ static void guc_mmio_reg_state_init(struct intel_guc *guc)
  {
    struct intel_gt *gt = guc_to_gt(guc);
    struct intel_engine_cs *engine;
    enum intel_engine_id id;
- 	struct temp_regset temp_set;
- 	struct guc_mmio_reg_set *ads_reg_set;
    u32 addr_ggtt, offset;
- 	u8 guc_class;
offset = guc_ads_regset_offset(guc);
    addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- 	temp_set.registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset);
- 	temp_set.size = guc->ads_regset_size / sizeof(temp_set.registers[0]);
+ 
+ 	iosys_map_memcpy_to(&guc->ads_map, offset, guc->ads_regset,
+ 			    guc->ads_regset_size);
for_each_engine(engine, gt, id) {
+ 		u32 count = guc->ads_regset_count[id];
+ 		u8 guc_class;
+ 
    	/* Class index is checked in class converter */
    	GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS);
guc_class = engine_class_to_guc_class(engine->class);
- 		ads_reg_set = &blob->ads.reg_state_list[guc_class][engine->instance];
- 		guc_mmio_regset_init(&temp_set, engine);
- 		if (!temp_set.used) {
- 			ads_reg_set->address = 0;
- 			ads_reg_set->count = 0;
+ 		if (!count) {
+ 			ads_blob_write(guc,
+ 				       ads.reg_state_list[guc_class][engine->instance].address,
+ 				       0);
+ 			ads_blob_write(guc,
+ 				       ads.reg_state_list[guc_class][engine->instance].count,
+ 				       0);
    		continue;
    	}
- 		ads_reg_set->address = addr_ggtt;
- 		ads_reg_set->count = temp_set.used;
+ 		ads_blob_write(guc,
+ 			       ads.reg_state_list[guc_class][engine->instance].address,
+ 			       addr_ggtt);
+ 		ads_blob_write(guc,
+ 			       ads.reg_state_list[guc_class][engine->instance].count,
+ 			       count);
- 		temp_set.size -= temp_set.used;
- 		temp_set.registers += temp_set.used;
- 		addr_ggtt += temp_set.used * sizeof(struct guc_mmio_reg);
+ 		addr_ggtt += count * sizeof(struct guc_mmio_reg);
    }
- 
- 	GEM_BUG_ON(temp_set.size);
  }
static void fill_engine_enable_masks(struct intel_gt *gt,
- 				     struct guc_gt_system_info *info)
+ 				     struct iosys_map *info_map)
  {
- 	info->engine_enabled_masks[GUC_RENDER_CLASS] = 1;
- 	info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1;
- 	info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt);
- 	info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt);
+ 	info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1);
+ 	info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt));
+ 	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
+ 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
+ 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
  }
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
  #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
- static int guc_prep_golden_context(struct intel_guc *guc,
- 				   struct __guc_ads_blob *blob)
+ static int guc_prep_golden_context(struct intel_guc *guc)
  {
    struct intel_gt *gt = guc_to_gt(guc);
    u32 addr_ggtt, offset;
    u32 total_size = 0, alloc_size, real_size;
    u8 engine_class, guc_class;
- 	struct guc_gt_system_info *info, local_info;
+ 	struct guc_gt_system_info local_info;
+ 	struct iosys_map info_map;
/*
     * Reserve the memory for the golden contexts and point GuC at it but
@@@ -375,14 -463,15 +463,15 @@@
     * GuC will also validate that the LRC base + size fall within the
     * allowed GGTT range.
     */
- 	if (blob) {
+ 	if (!iosys_map_is_null(&guc->ads_map)) {
    	offset = guc_ads_golden_ctxt_offset(guc);
    	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- 		info = &blob->system_info;
+ 		info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map,
+ 						 offsetof(struct __guc_ads_blob, system_info));
    } else {
    	memset(&local_info, 0, sizeof(local_info));
- 		info = &local_info;
- 		fill_engine_enable_masks(gt, info);
+ 		iosys_map_set_vaddr(&info_map, &local_info);
+ 		fill_engine_enable_masks(gt, &info_map);
    }
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
@@@ -391,14 -480,14 +480,14 @@@
guc_class = engine_class_to_guc_class(engine_class);
- 		if (!info->engine_enabled_masks[guc_class])
+ 		if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
    		continue;
real_size = intel_engine_context_size(gt, engine_class);
    	alloc_size = PAGE_ALIGN(real_size);
    	total_size += alloc_size;
- 		if (!blob)
+ 		if (iosys_map_is_null(&guc->ads_map))
    		continue;
/*
@@@ -412,15 -501,18 +501,18 @@@
    	 * what comes before it in the context image (which is identical
    	 * on all engines).
    	 */
- 		blob->ads.eng_state_size[guc_class] = real_size - LRC_SKIP_SIZE;
- 		blob->ads.golden_context_lrca[guc_class] = addr_ggtt;
+ 		ads_blob_write(guc, ads.eng_state_size[guc_class],
+ 			       real_size - LRC_SKIP_SIZE);
+ 		ads_blob_write(guc, ads.golden_context_lrca[guc_class],
+ 			       addr_ggtt);
+ 
    	addr_ggtt += alloc_size;
    }
- 	if (!blob)
- 		return total_size;
+ 	/* Make sure current size matches what we calculated previously */
+ 	if (guc->ads_golden_ctxt_size)
+ 		GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
- 	GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
    return total_size;
  }
@@@ -444,18 -536,16 +536,16 @@@ static struct intel_engine_cs *find_eng
static void guc_init_golden_context(struct intel_guc *guc)
  {
- 	struct __guc_ads_blob *blob = guc->ads_blob;
    struct intel_engine_cs *engine;
    struct intel_gt *gt = guc_to_gt(guc);
- 	u32 addr_ggtt, offset;
- 	u32 total_size = 0, alloc_size, real_size;
+ 	unsigned long offset;
+ 	u32 addr_ggtt, total_size = 0, alloc_size, real_size;
    u8 engine_class, guc_class;
- 	u8 *ptr;
if (!intel_uc_uses_guc_submission(&gt->uc))
    	return;
- 	GEM_BUG_ON(!blob);
+ 	GEM_BUG_ON(iosys_map_is_null(&guc->ads_map));
/*
     * Go back and fill in the golden context data now that it is
@@@ -463,15 -553,13 +553,13 @@@
     */
    offset = guc_ads_golden_ctxt_offset(guc);
    addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- 	ptr = ((u8 *)blob) + offset;
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
    	if (engine_class == OTHER_CLASS)
    		continue;
guc_class = engine_class_to_guc_class(engine_class);
- 
- 		if (!blob->system_info.engine_enabled_masks[guc_class])
+ 		if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
    		continue;
real_size = intel_engine_context_size(gt, engine_class);
@@@ -482,65 -570,95 +570,95 @@@
    	if (!engine) {
    		drm_err(&gt->i915->drm, "No engine state recorded for class %d!\n",
    			engine_class);
- 			blob->ads.eng_state_size[guc_class] = 0;
- 			blob->ads.golden_context_lrca[guc_class] = 0;
+ 			ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
+ 			ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0);
    		continue;
    	}
- 		GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+ 		GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) !=
    		   real_size - LRC_SKIP_SIZE);
- 		GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] != addr_ggtt);
+ 		GEM_BUG_ON(ads_blob_read(guc, ads.golden_context_lrca[guc_class]) != addr_ggtt);
+ 
    	addr_ggtt += alloc_size;
- 		shmem_read(engine->default_state, 0, ptr, real_size);
- 		ptr += alloc_size;
+ 		shmem_read_to_iosys_map(engine->default_state, 0, &guc->ads_map,
+ 					offset, real_size);
+ 		offset += alloc_size;
    }
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
  }
+ static void guc_capture_list_init(struct intel_guc *guc)
+ {
+ 	int i, j;
+ 	u32 addr_ggtt, offset;
+ 
+ 	offset = guc_ads_capture_offset(guc);
+ 	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
+ 
+ 	/* FIXME: Populate a proper capture list */
+ 
+ 	for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
+ 		for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
+ 			ads_blob_write(guc, ads.capture_instance[i][j], addr_ggtt);
+ 			ads_blob_write(guc, ads.capture_class[i][j], addr_ggtt);
+ 		}
+ 
+ 		ads_blob_write(guc, ads.capture_global[i], addr_ggtt);
+ 	}
+ }
+ 
  static void __guc_ads_init(struct intel_guc *guc)
  {
    struct intel_gt *gt = guc_to_gt(guc);
    struct drm_i915_private *i915 = gt->i915;
- 	struct __guc_ads_blob *blob = guc->ads_blob;
+ 	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map,
+ 			offsetof(struct __guc_ads_blob, system_info));
    u32 base;
/* GuC scheduling policies */
- 	guc_policies_init(guc, &blob->policies);
+ 	guc_policies_init(guc);
/* System info */
- 	fill_engine_enable_masks(gt, &blob->system_info);
+ 	fill_engine_enable_masks(gt, &info_map);
- 	blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] =
- 		hweight8(gt->info.sseu.slice_mask);
- 	blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
- 		gt->info.vdbox_sfc_access;
+ 	ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED],
+ 		       hweight8(gt->info.sseu.slice_mask));
+ 	ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK],
+ 		       gt->info.vdbox_sfc_access);
if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
    	u32 distdbreg = intel_uncore_read(gt->uncore,
    					  GEN12_DIST_DBS_POPULATED);
- 		blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
- 			((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) &
- 			 GEN12_DOORBELLS_PER_SQIDI) + 1;
+ 		ads_blob_write(guc,
+ 			       system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
+ 			       ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT)
+ 				& GEN12_DOORBELLS_PER_SQIDI) + 1);
    }
/* Golden contexts for re-initialising after a watchdog reset */
- 	guc_prep_golden_context(guc, blob);
+ 	guc_prep_golden_context(guc);
- 	guc_mapping_table_init(guc_to_gt(guc), &blob->system_info);
+ 	guc_mapping_table_init(guc_to_gt(guc), &info_map);
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
+ 	/* Capture list for hang debug */
+ 	guc_capture_list_init(guc);
+ 
    /* ADS */
- 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- 	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
+ 	ads_blob_write(guc, ads.scheduler_policies, base +
+ 		       offsetof(struct __guc_ads_blob, policies));
+ 	ads_blob_write(guc, ads.gt_system_info, base +
+ 		       offsetof(struct __guc_ads_blob, system_info));
/* MMIO save/restore list */
- 	guc_mmio_reg_state_init(guc, blob);
+ 	guc_mmio_reg_state_init(guc);
/* Private Data */
- 	blob->ads.private_data = base + guc_ads_private_data_offset(guc);
+ 	ads_blob_write(guc, ads.private_data, base +
+ 		       guc_ads_private_data_offset(guc));
i915_gem_object_flush_map(guc->ads_vma->obj);
  }
@@@ -554,19 -672,23 +672,23 @@@
   */
  int intel_guc_ads_create(struct intel_guc *guc)
  {
+ 	void *ads_blob;
    u32 size;
    int ret;
GEM_BUG_ON(guc->ads_vma);
- 	/* Need to calculate the reg state size dynamically: */
- 	ret = guc_mmio_reg_state_query(guc);
+ 	/*
+ 	 * Create reg state size dynamically on system memory to be copied to
+ 	 * the final ads blob on gt init/reset
+ 	 */
+ 	ret = guc_mmio_reg_state_create(guc);
    if (ret < 0)
    	return ret;
    guc->ads_regset_size = ret;
/* Likewise the golden contexts: */
- 	ret = guc_prep_golden_context(guc, NULL);
+ 	ret = guc_prep_golden_context(guc);
    if (ret < 0)
    	return ret;
    guc->ads_golden_ctxt_size = ret;
@@@ -575,10 -697,15 +697,15 @@@
    size = guc_ads_blob_size(guc);
ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma,
- 					     (void **)&guc->ads_blob);
+ 					     &ads_blob);
    if (ret)
    	return ret;
+ 	if (i915_gem_object_is_lmem(guc->ads_vma->obj))
+ 		iosys_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)ads_blob);
+ 	else
+ 		iosys_map_set_vaddr(&guc->ads_map, ads_blob);
+ 
    __guc_ads_init(guc);
return 0;
@@@ -599,7 -726,8 +726,8 @@@ void intel_guc_ads_init_late(struct int
  void intel_guc_ads_destroy(struct intel_guc *guc)
  {
    i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP);
- 	guc->ads_blob = NULL;
+ 	iosys_map_clear(&guc->ads_map);
+ 	kfree(guc->ads_regset);
  }
static void guc_ads_private_data_reset(struct intel_guc *guc)
@@@ -610,8 -738,8 +738,8 @@@
    if (!size)
    	return;
- 	memset((void *)guc->ads_blob + guc_ads_private_data_offset(guc), 0,
- 	       size);
+ 	iosys_map_memset(&guc->ads_map, guc_ads_private_data_offset(guc),
+ 			 0, size);
  }
/**
@@@ -634,18 -762,16 +762,16 @@@ void intel_guc_ads_reset(struct intel_g
u32 intel_guc_engine_usage_offset(struct intel_guc *guc)
  {
- 	struct __guc_ads_blob *blob = guc->ads_blob;
- 	u32 base = intel_guc_ggtt_offset(guc, guc->ads_vma);
- 	u32 offset = base + ptr_offset(blob, engine_usage);
- 
- 	return offset;
+ 	return intel_guc_ggtt_offset(guc, guc->ads_vma) +
+ 		offsetof(struct __guc_ads_blob, engine_usage);
  }
- struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs *engine)
+ struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine)
  {
    struct intel_guc *guc = &engine->gt->uc.guc;
- 	struct __guc_ads_blob *blob = guc->ads_blob;
    u8 guc_class = engine_class_to_guc_class(engine->class);
+ 	size_t offset = offsetof(struct __guc_ads_blob,
+ 				 engine_usage.engines[guc_class][ilog2(engine->logical_mask)]);
- 	return &blob->engine_usage.engines[guc_class][ilog2(engine->logical_mask)];
+ 	return IOSYS_MAP_INIT_OFFSET(&guc->ads_map, offset);
  }
diff --combined drivers/gpu/drm/i915/i915_reg.h
index 902e4c802a12,4da10e131216..3c87d77d2cf6
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -25,8 -25,7 +25,7 @@@
  #ifndef _I915_REG_H_
  #define _I915_REG_H_
- #include <linux/bitfield.h>
- #include <linux/bits.h>
+ #include "i915_reg_defs.h"
/**
   * DOC: The i915 register macro definition style guide
@@@ -116,95 -115,6 +115,6 @@@
   *  #define GEN8_BAR                    _MMIO(0xb888)
   */
- /**
-  * REG_BIT() - Prepare a u32 bit value
-  * @__n: 0-based bit number
-  *
-  * Local wrapper for BIT() to force u32, with compile time checks.
-  *
-  * @return: Value with bit @__n set.
-  */
- #define REG_BIT(__n)							\
- 	((u32)(BIT(__n) +						\
- 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
- 				 ((__n) < 0 || (__n) > 31))))
- 
- /**
-  * REG_GENMASK() - Prepare a continuous u32 bitmask
-  * @__high: 0-based high bit
-  * @__low: 0-based low bit
-  *
-  * Local wrapper for GENMASK() to force u32, with compile time checks.
-  *
-  * @return: Continuous bitmask from @__high to @__low, inclusive.
-  */
- #define REG_GENMASK(__high, __low)					\
- 	((u32)(GENMASK(__high, __low) +					\
- 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
- 				 __is_constexpr(__low) &&		\
- 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
- 
- /*
-  * Local integer constant expression version of is_power_of_2().
-  */
- #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
- 
- /**
-  * REG_FIELD_PREP() - Prepare a u32 bitfield value
-  * @__mask: shifted mask defining the field's length and position
-  * @__val: value to put in the field
-  *
-  * Local copy of FIELD_PREP() to generate an integer constant expression, force
-  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
-  *
-  * @return: @__val masked and shifted into the field defined by @__mask.
-  */
- #define REG_FIELD_PREP(__mask, __val)						\
- 	((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +	\
- 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +		\
- 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
- 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
- 
- /**
-  * REG_FIELD_GET() - Extract a u32 bitfield value
-  * @__mask: shifted mask defining the field's length and position
-  * @__val: value to extract the bitfield value from
-  *
-  * Local wrapper for FIELD_GET() to force u32 and for consistency with
-  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
-  *
-  * @return: Masked and shifted value of the field defined by @__mask in @__val.
-  */
- #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
- 
- typedef struct {
- 	u32 reg;
- } i915_reg_t;
- 
- #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
- 
- #define INVALID_MMIO_REG _MMIO(0)
- 
- static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
- {
- 	return reg.reg;
- }
- 
- static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
- {
- 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
- }
- 
- static inline bool i915_mmio_reg_valid(i915_reg_t reg)
- {
- 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
- }
- 
- #define VLV_DISPLAY_BASE		0x180000
- #define VLV_MIPI_BASE			VLV_DISPLAY_BASE
- #define BXT_MIPI_BASE			0x60000
- 
  #define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display_mmio_offset)
/*
@@@ -275,247 -185,6 +185,6 @@@
  #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
  #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
- /* PCI config space */
- 
- #define MCHBAR_I915 0x44
- #define MCHBAR_I965 0x48
- #define MCHBAR_SIZE (4 * 4096)
- 
- #define DEVEN 0x54
- #define   DEVEN_MCHBAR_EN (1 << 28)
- 
- /* BSM in include/drm/i915_drm.h */
- 
- #define HPLLCC	0xc0 /* 85x only */
- #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
- #define   GC_CLOCK_133_200		(0 << 0)
- #define   GC_CLOCK_100_200		(1 << 0)
- #define   GC_CLOCK_100_133		(2 << 0)
- #define   GC_CLOCK_133_266		(3 << 0)
- #define   GC_CLOCK_133_200_2		(4 << 0)
- #define   GC_CLOCK_133_266_2		(5 << 0)
- #define   GC_CLOCK_166_266		(6 << 0)
- #define   GC_CLOCK_166_250		(7 << 0)
- 
- #define I915_GDRST 0xc0 /* PCI config register */
- #define   GRDOM_FULL		(0 << 2)
- #define   GRDOM_RENDER		(1 << 2)
- #define   GRDOM_MEDIA		(3 << 2)
- #define   GRDOM_MASK		(3 << 2)
- #define   GRDOM_RESET_STATUS	(1 << 1)
- #define   GRDOM_RESET_ENABLE	(1 << 0)
- 
- /* BSpec only has register offset, PCI device and bit found empirically */
- #define I830_CLOCK_GATE	0xc8 /* device 0 */
- #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
- 
- #define GCDGMBUS 0xcc
- 
- #define GCFGC2	0xda
- #define GCFGC	0xf0 /* 915+ only */
- #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
- #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
- #define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
- #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
- #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
- #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
- #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
- #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
- #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
- #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
- #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
- #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
- #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
- #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
- #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
- #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
- #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
- #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
- #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
- #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
- #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
- #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
- #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
- #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
- #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
- #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
- #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
- #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
- #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
- 
- #define ASLE	0xe4
- #define ASLS	0xfc
- 
- #define SWSCI	0xe8
- #define   SWSCI_SCISEL	(1 << 15)
- #define   SWSCI_GSSCIE	(1 << 0)
- 
- #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
- 
- 
- #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
- #define  ILK_GRDOM_FULL		(0 << 1)
- #define  ILK_GRDOM_RENDER	(1 << 1)
- #define  ILK_GRDOM_MEDIA	(3 << 1)
- #define  ILK_GRDOM_MASK		(3 << 1)
- #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
- 
- #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
- #define   GEN6_MBC_SNPCR_SHIFT	21
- #define   GEN6_MBC_SNPCR_MASK	(3 << 21)
- #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
- #define   GEN6_MBC_SNPCR_MED	(1 << 21)
- #define   GEN6_MBC_SNPCR_LOW	(2 << 21)
- #define   GEN6_MBC_SNPCR_MIN	(3 << 21) /* only 1/16th of the cache is shared */
- 
- #define VLV_G3DCTL		_MMIO(0x9024)
- #define VLV_GSCKGCTL		_MMIO(0x9028)
- 
- #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
- #define   FBC_LLC_FULLY_OPEN	REG_BIT(30)
- 
- #define GEN6_MBCTL		_MMIO(0x0907c)
- #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
- #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
- #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
- #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
- #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
- 
- #define GEN6_GDRST	_MMIO(0x941c)
- #define  GEN6_GRDOM_FULL		(1 << 0)
- #define  GEN6_GRDOM_RENDER		(1 << 1)
- #define  GEN6_GRDOM_MEDIA		(1 << 2)
- #define  GEN6_GRDOM_BLT			(1 << 3)
- #define  GEN6_GRDOM_VECS		(1 << 4)
- #define  GEN9_GRDOM_GUC			(1 << 5)
- #define  GEN8_GRDOM_MEDIA2		(1 << 7)
- /* GEN11 changed all bit defs except for FULL & RENDER */
- #define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
- #define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
- #define  GEN11_GRDOM_BLT		(1 << 2)
- #define  GEN11_GRDOM_GUC		(1 << 3)
- #define  GEN11_GRDOM_MEDIA		(1 << 5)
- #define  GEN11_GRDOM_MEDIA2		(1 << 6)
- #define  GEN11_GRDOM_MEDIA3		(1 << 7)
- #define  GEN11_GRDOM_MEDIA4		(1 << 8)
- #define  GEN11_GRDOM_MEDIA5		(1 << 9)
- #define  GEN11_GRDOM_MEDIA6		(1 << 10)
- #define  GEN11_GRDOM_MEDIA7		(1 << 11)
- #define  GEN11_GRDOM_MEDIA8		(1 << 12)
- #define  GEN11_GRDOM_VECS		(1 << 13)
- #define  GEN11_GRDOM_VECS2		(1 << 14)
- #define  GEN11_GRDOM_VECS3		(1 << 15)
- #define  GEN11_GRDOM_VECS4		(1 << 16)
- #define  GEN11_GRDOM_SFC0		(1 << 17)
- #define  GEN11_GRDOM_SFC1		(1 << 18)
- #define  GEN11_GRDOM_SFC2		(1 << 19)
- #define  GEN11_GRDOM_SFC3		(1 << 20)
- 
- #define  GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
- #define  GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
- 
- #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
- #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
- #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
- #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
- #define   GEN11_VCS_SFC_LOCK_ACK_BIT		(1 << 1)
- 
- #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
- #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
- #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
- #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
- #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
- #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
- 
- #define GEN12_HCP_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x2910)
- #define   GEN12_HCP_SFC_FORCED_LOCK_BIT		REG_BIT(0)
- #define GEN12_HCP_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x2914)
- #define   GEN12_HCP_SFC_LOCK_ACK_BIT		REG_BIT(1)
- #define   GEN12_HCP_SFC_USAGE_BIT			REG_BIT(0)
- 
- #define GEN12_SFC_DONE(n)		_MMIO(0x1cc000 + (n) * 0x1000)
- #define GEN12_SFC_DONE_MAX		4
- 
- #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
- #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
- #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
- #define   PP_DIR_DCLV_2G		0xffffffff
- 
- #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
- #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
- 
- #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
- #define   GEN8_RPCS_ENABLE		(1 << 31)
- #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
- #define   GEN8_RPCS_S_CNT_SHIFT		15
- #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
- #define   GEN11_RPCS_S_CNT_SHIFT	12
- #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
- #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
- #define   GEN8_RPCS_SS_CNT_SHIFT	8
- #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
- #define   GEN8_RPCS_EU_MAX_SHIFT	4
- #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
- #define   GEN8_RPCS_EU_MIN_SHIFT	0
- #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
- 
- #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
- /* HSW only */
- #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
- #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
- #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
- #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
- /* HSW+ */
- #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
- #define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
- #define   HSW_RCS_INHIBIT				(1 << 8)
- /* Gen8 */
- #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
- #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
- #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
- #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
- #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
- #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
- #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
- #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
- #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
- #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
- 
- #define GAM_ECOCHK			_MMIO(0x4090)
- #define   BDW_DISABLE_HDC_INVALIDATION	(1 << 25)
- #define   ECOCHK_SNB_BIT		(1 << 10)
- #define   ECOCHK_DIS_TLB		(1 << 8)
- #define   HSW_ECOCHK_ARB_PRIO_SOL	(1 << 6)
- #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
- #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
- #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
- #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
- #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
- #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
- #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
- 
- #define GEN8_RC6_CTX_INFO		_MMIO(0x8504)
- 
- #define GAC_ECO_BITS			_MMIO(0x14090)
- #define   ECOBITS_SNB_BIT		(1 << 13)
- #define   ECOBITS_PPGTT_CACHE64B	(3 << 8)
- #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
- 
- #define GEN12_GAMCNTRL_CTRL			_MMIO(0xcf54)
- #define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
- #define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
- 
- #define GEN12_GAMSTLB_CTRL		_MMIO(0xcf4c)
- #define   CONTROL_BLOCK_CLKGATE_DIS	REG_BIT(12)
- #define   EGRESS_BLOCK_CLKGATE_DIS	REG_BIT(11)
- #define   TAG_BLOCK_CLKGATE_DIS		REG_BIT(7)
- 
- #define GEN12_MERT_MOD_CTRL		_MMIO(0xcf28)
- #define   FORCE_MISS_FTLB		REG_BIT(3)
- 
- #define GAB_CTL				_MMIO(0x24000)
- #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1 << 8)
- 
  #define GU_CNTL				_MMIO(0x101010)
  #define   LMEM_INIT			REG_BIT(7)
@@@ -538,671 -207,7 +207,7 @@@
  #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
  #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
- /* VGA stuff */
- 
- #define VGA_ST01_MDA 0x3ba
- #define VGA_ST01_CGA 0x3da
- 
  #define _VGA_MSR_WRITE _MMIO(0x3c2)
- #define VGA_MSR_WRITE 0x3c2
- #define VGA_MSR_READ 0x3cc
- #define   VGA_MSR_MEM_EN (1 << 1)
- #define   VGA_MSR_CGA_MODE (1 << 0)
- 
- #define VGA_SR_INDEX 0x3c4
- #define SR01			1
- #define VGA_SR_DATA 0x3c5
- 
- #define VGA_AR_INDEX 0x3c0
- #define   VGA_AR_VID_EN (1 << 5)
- #define VGA_AR_DATA_WRITE 0x3c0
- #define VGA_AR_DATA_READ 0x3c1
- 
- #define VGA_GR_INDEX 0x3ce
- #define VGA_GR_DATA 0x3cf
- /* GR05 */
- #define   VGA_GR_MEM_READ_MODE_SHIFT 3
- #define     VGA_GR_MEM_READ_MODE_PLANE 1
- /* GR06 */
- #define   VGA_GR_MEM_MODE_MASK 0xc
- #define   VGA_GR_MEM_MODE_SHIFT 2
- #define   VGA_GR_MEM_A0000_AFFFF 0
- #define   VGA_GR_MEM_A0000_BFFFF 1
- #define   VGA_GR_MEM_B0000_B7FFF 2
- #define   VGA_GR_MEM_B0000_BFFFF 3
- 
- #define VGA_DACMASK 0x3c6
- #define VGA_DACRX 0x3c7
- #define VGA_DACWX 0x3c8
- #define VGA_DACDATA 0x3c9
- 
- #define VGA_CR_INDEX_MDA 0x3b4
- #define VGA_CR_DATA_MDA 0x3b5
- #define VGA_CR_INDEX_CGA 0x3d4
- #define VGA_CR_DATA_CGA 0x3d5
- 
- #define MI_PREDICATE_SRC0	_MMIO(0x2400)
- #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
- #define MI_PREDICATE_SRC1	_MMIO(0x2408)
- #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
- #define MI_PREDICATE_DATA       _MMIO(0x2410)
- #define MI_PREDICATE_RESULT     _MMIO(0x2418)
- #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
- #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
- #define  LOWER_SLICE_ENABLED	(1 << 0)
- #define  LOWER_SLICE_DISABLED	(0 << 0)
- 
- /*
-  * Registers used only by the command parser
-  */
- #define BCS_SWCTRL _MMIO(0x22200)
- #define   BCS_SRC_Y REG_BIT(0)
- #define   BCS_DST_Y REG_BIT(1)
- 
- /* There are 16 GPR registers */
- #define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)
- #define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)
- 
- #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
- #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
- #define HS_INVOCATION_COUNT             _MMIO(0x2300)
- #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
- #define DS_INVOCATION_COUNT             _MMIO(0x2308)
- #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
- #define IA_VERTICES_COUNT               _MMIO(0x2310)
- #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
- #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
- #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
- #define VS_INVOCATION_COUNT             _MMIO(0x2320)
- #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
- #define GS_INVOCATION_COUNT             _MMIO(0x2328)
- #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
- #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
- #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
- #define CL_INVOCATION_COUNT             _MMIO(0x2338)
- #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
- #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
- #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
- #define PS_INVOCATION_COUNT             _MMIO(0x2348)
- #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
- #define PS_DEPTH_COUNT                  _MMIO(0x2350)
- #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
- 
- /* There are the 4 64-bit counter registers, one for each stream output */
- #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
- #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
- 
- #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
- #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
- 
- #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
- #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
- #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
- #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
- #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
- #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
- 
- #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
- #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
- #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
- 
- /* There are the 16 64-bit CS General Purpose Registers */
- #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
- #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
- 
- #define GEN7_OACONTROL _MMIO(0x2360)
- #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
- #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
- #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
- #define  GEN7_OACONTROL_TIMER_ENABLE	    (1 << 5)
- #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
- #define  GEN7_OACONTROL_FORMAT_A29	    (1 << 2)
- #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
- #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
- #define  GEN7_OACONTROL_FORMAT_B4_C8	    (4 << 2)
- #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
- #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
- #define  GEN7_OACONTROL_FORMAT_C4_B8	    (7 << 2)
- #define  GEN7_OACONTROL_FORMAT_SHIFT	    2
- #define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1 << 1)
- #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
- 
- #define GEN8_OACTXID _MMIO(0x2364)
- 
- #define GEN8_OA_DEBUG _MMIO(0x2B04)
- #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
- #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1 << 6)
- #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1 << 2)
- #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
- 
- #define GEN8_OACONTROL _MMIO(0x2B00)
- #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
- #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
- #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
- #define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7 << 2)
- #define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
- #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
- #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
- 
- #define GEN8_OACTXCONTROL _MMIO(0x2360)
- #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
- #define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
- #define  GEN8_OA_TIMER_ENABLE		    (1 << 1)
- #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
- 
- #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
- #define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1 << 3)
- #define  GEN7_OABUFFER_EDGE_TRIGGER	    (1 << 2)
- #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
- #define  GEN7_OABUFFER_RESUME		    (1 << 0)
- 
- #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
- #define GEN8_OABUFFER _MMIO(0x2b14)
- #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
- 
- #define GEN7_OASTATUS1 _MMIO(0x2364)
- #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
- #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
- #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
- #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
- 
- #define GEN7_OASTATUS2 _MMIO(0x2368)
- #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
- #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
- 
- #define GEN8_OASTATUS _MMIO(0x2b08)
- #define  GEN8_OASTATUS_TAIL_POINTER_WRAP    (1 << 17)
- #define  GEN8_OASTATUS_HEAD_POINTER_WRAP    (1 << 16)
- #define  GEN8_OASTATUS_OVERRUN_STATUS	    (1 << 3)
- #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
- #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
- #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
- 
- #define GEN8_OAHEADPTR _MMIO(0x2B0C)
- #define GEN8_OAHEADPTR_MASK    0xffffffc0
- #define GEN8_OATAILPTR _MMIO(0x2B10)
- #define GEN8_OATAILPTR_MASK    0xffffffc0
- 
- #define OABUFFER_SIZE_128K  (0 << 3)
- #define OABUFFER_SIZE_256K  (1 << 3)
- #define OABUFFER_SIZE_512K  (2 << 3)
- #define OABUFFER_SIZE_1M    (3 << 3)
- #define OABUFFER_SIZE_2M    (4 << 3)
- #define OABUFFER_SIZE_4M    (5 << 3)
- #define OABUFFER_SIZE_8M    (6 << 3)
- #define OABUFFER_SIZE_16M   (7 << 3)
- 
- #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
- 
- #define GEN12_SQCM		_MMIO(0x8724)
- #define   EN_32B_ACCESS		REG_BIT(30)
- 
- /* Gen12 OAR unit */
- #define GEN12_OAR_OACONTROL _MMIO(0x2960)
- #define  GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
- #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
- 
- #define GEN12_OACTXCONTROL _MMIO(0x2360)
- #define GEN12_OAR_OASTATUS _MMIO(0x2968)
- 
- /* Gen12 OAG unit */
- #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
- #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
- #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
- #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
- 
- #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
- #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
- #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
- #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
- 
- #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
- #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
- #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE       (1 << 1)
- #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
- 
- #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
- #define  GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
- #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
- 
- #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
- #define  GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO          (1 << 6)
- #define  GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS  (1 << 5)
- #define  GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS     (1 << 2)
- #define  GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
- 
- #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
- #define  GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
- #define  GEN12_OAG_OASTATUS_BUFFER_OVERFLOW  (1 << 1)
- #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
- 
- /*
-  * Flexible, Aggregate EU Counter Registers.
-  * Note: these aren't contiguous
-  */
- #define EU_PERF_CNTL0	    _MMIO(0xe458)
- #define EU_PERF_CNTL1	    _MMIO(0xe558)
- #define EU_PERF_CNTL2	    _MMIO(0xe658)
- #define EU_PERF_CNTL3	    _MMIO(0xe758)
- #define EU_PERF_CNTL4	    _MMIO(0xe45c)
- #define EU_PERF_CNTL5	    _MMIO(0xe55c)
- #define EU_PERF_CNTL6	    _MMIO(0xe65c)
- 
- #define RT_CTRL			_MMIO(0xe530)
- #define  DIS_NULL_QUERY		REG_BIT(10)
- 
- /*
-  * OA Boolean state
-  */
- 
- #define OASTARTTRIG1 _MMIO(0x2710)
- #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
- #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
- 
- #define OASTARTTRIG2 _MMIO(0x2714)
- #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
- #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
- #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
- #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
- #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
- #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
- #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
- #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
- #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
- #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
- #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
- #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
- #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
- #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
- #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
- #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
- #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
- #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
- #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
- #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
- #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
- #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
- #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
- #define OASTARTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
- #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
- #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
- #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
- #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
- #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
- 
- #define OASTARTTRIG3 _MMIO(0x2718)
- #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
- #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
- #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
- #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
- #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
- #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
- #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
- #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
- #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
- 
- #define OASTARTTRIG4 _MMIO(0x271c)
- #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
- #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
- #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
- #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
- #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
- #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
- #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
- #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
- #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
- 
- #define OASTARTTRIG5 _MMIO(0x2720)
- #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
- #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
- 
- #define OASTARTTRIG6 _MMIO(0x2724)
- #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
- #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
- #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
- #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
- #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
- #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
- #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
- #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
- #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
- #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
- #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
- #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
- #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
- #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
- #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
- #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
- #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
- #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
- #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
- #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
- #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
- #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
- #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
- #define OASTARTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
- #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
- #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
- #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
- #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
- #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
- 
- #define OASTARTTRIG7 _MMIO(0x2728)
- #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
- #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
- #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
- #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
- #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
- #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
- #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
- #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
- #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
- 
- #define OASTARTTRIG8 _MMIO(0x272c)
- #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
- #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
- #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
- #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
- #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
- #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
- #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
- #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
- #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
- 
- #define OAREPORTTRIG1 _MMIO(0x2740)
- #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
- #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
- 
- #define OAREPORTTRIG2 _MMIO(0x2744)
- #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
- #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
- #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
- #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
- #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
- #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
- #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
- #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
- #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
- #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
- #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
- #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
- #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
- #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
- #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
- #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
- #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
- #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
- #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
- #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
- #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
- #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
- #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
- #define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
- #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
- 
- #define OAREPORTTRIG3 _MMIO(0x2748)
- #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
- #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
- #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
- #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
- #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
- #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
- #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
- #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
- #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
- 
- #define OAREPORTTRIG4 _MMIO(0x274c)
- #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
- #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
- #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
- #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
- #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
- #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
- #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
- #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
- #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
- 
- #define OAREPORTTRIG5 _MMIO(0x2750)
- #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
- #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
- 
- #define OAREPORTTRIG6 _MMIO(0x2754)
- #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
- #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
- #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
- #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
- #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
- #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
- #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
- #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
- #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
- #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
- #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
- #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
- #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
- #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
- #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
- #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
- #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
- #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
- #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
- #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
- #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
- #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
- #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
- #define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
- #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
- 
- #define OAREPORTTRIG7 _MMIO(0x2758)
- #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
- #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
- #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
- #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
- #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
- #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
- #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
- #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
- #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
- 
- #define OAREPORTTRIG8 _MMIO(0x275c)
- #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
- #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
- #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
- #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
- #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
- #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
- #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
- #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
- #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
- 
- /* Same layout as OASTARTTRIGX */
- #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
- #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
- #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
- #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
- #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
- #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
- #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
- #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
- 
- /* Same layout as OAREPORTTRIGX */
- #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
- #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
- #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
- #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
- #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
- #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
- #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
- #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
- 
- /* CECX_0 */
- #define OACEC_COMPARE_LESS_OR_EQUAL	6
- #define OACEC_COMPARE_NOT_EQUAL		5
- #define OACEC_COMPARE_LESS_THAN		4
- #define OACEC_COMPARE_GREATER_OR_EQUAL	3
- #define OACEC_COMPARE_EQUAL		2
- #define OACEC_COMPARE_GREATER_THAN	1
- #define OACEC_COMPARE_ANY_EQUAL		0
- 
- #define OACEC_COMPARE_VALUE_MASK    0xffff
- #define OACEC_COMPARE_VALUE_SHIFT   3
- 
- #define OACEC_SELECT_NOA	(0 << 19)
- #define OACEC_SELECT_PREV	(1 << 19)
- #define OACEC_SELECT_BOOLEAN	(2 << 19)
- 
- /* 11-bit array 0: pass-through, 1: negated */
- #define GEN12_OASCEC_NEGATE_MASK  0x7ff
- #define GEN12_OASCEC_NEGATE_SHIFT 21
- 
- /* CECX_1 */
- #define OACEC_MASK_MASK		    0xffff
- #define OACEC_CONSIDERATIONS_MASK   0xffff
- #define OACEC_CONSIDERATIONS_SHIFT  16
- 
- #define OACEC0_0 _MMIO(0x2770)
- #define OACEC0_1 _MMIO(0x2774)
- #define OACEC1_0 _MMIO(0x2778)
- #define OACEC1_1 _MMIO(0x277c)
- #define OACEC2_0 _MMIO(0x2780)
- #define OACEC2_1 _MMIO(0x2784)
- #define OACEC3_0 _MMIO(0x2788)
- #define OACEC3_1 _MMIO(0x278c)
- #define OACEC4_0 _MMIO(0x2790)
- #define OACEC4_1 _MMIO(0x2794)
- #define OACEC5_0 _MMIO(0x2798)
- #define OACEC5_1 _MMIO(0x279c)
- #define OACEC6_0 _MMIO(0x27a0)
- #define OACEC6_1 _MMIO(0x27a4)
- #define OACEC7_0 _MMIO(0x27a8)
- #define OACEC7_1 _MMIO(0x27ac)
- 
- /* Same layout as CECX_Y */
- #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
- #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
- #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
- #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
- #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
- #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
- #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
- #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
- #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
- #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
- #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
- #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
- #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
- #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
- #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
- #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
- 
- /* Same layout as CECX_Y + negate 11-bit array */
- #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
- #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
- #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
- #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
- #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
- #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
- #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
- #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
- #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
- #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
- #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
- #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
- #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
- #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
- #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
- #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
- 
- /* OA perf counters */
- #define OA_PERFCNT1_LO      _MMIO(0x91B8)
- #define OA_PERFCNT1_HI      _MMIO(0x91BC)
- #define OA_PERFCNT2_LO      _MMIO(0x91C0)
- #define OA_PERFCNT2_HI      _MMIO(0x91C4)
- #define OA_PERFCNT3_LO      _MMIO(0x91C8)
- #define OA_PERFCNT3_HI      _MMIO(0x91CC)
- #define OA_PERFCNT4_LO      _MMIO(0x91D8)
- #define OA_PERFCNT4_HI      _MMIO(0x91DC)
- 
- #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
- #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
- 
- /* RPM unit config (Gen8+) */
- #define RPM_CONFIG0	    _MMIO(0x0D00)
- #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
- #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
- #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
- #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
- #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
- #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
- #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
- 
- #define RPM_CONFIG1	    _MMIO(0x0D04)
- #define  GEN10_GT_NOA_ENABLE  (1 << 9)
- 
- /* GPM unit config (Gen9+) */
- #define CTC_MODE			_MMIO(0xA26C)
- #define  CTC_SOURCE_PARAMETER_MASK 1
- #define  CTC_SOURCE_CRYSTAL_CLOCK	0
- #define  CTC_SOURCE_DIVIDE_LOGIC	1
- #define  CTC_SHIFT_PARAMETER_SHIFT	1
- #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
- 
- /* RCP unit config (Gen8+) */
- #define RCP_CONFIG	    _MMIO(0x0D08)
- 
- /* NOA (HSW) */
- #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
- #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
- #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
- #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
- #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
- #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
- #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
- #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
- #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
- #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
- 
- #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
- 
- /* NOA (Gen8+) */
- #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
- 
- #define MICRO_BP0_0	    _MMIO(0x9800)
- #define MICRO_BP0_2	    _MMIO(0x9804)
- #define MICRO_BP0_1	    _MMIO(0x9808)
- 
- #define MICRO_BP1_0	    _MMIO(0x980C)
- #define MICRO_BP1_2	    _MMIO(0x9810)
- #define MICRO_BP1_1	    _MMIO(0x9814)
- 
- #define MICRO_BP2_0	    _MMIO(0x9818)
- #define MICRO_BP2_2	    _MMIO(0x981C)
- #define MICRO_BP2_1	    _MMIO(0x9820)
- 
- #define MICRO_BP3_0	    _MMIO(0x9824)
- #define MICRO_BP3_2	    _MMIO(0x9828)
- #define MICRO_BP3_1	    _MMIO(0x982C)
- 
- #define MICRO_BP_TRIGGER		_MMIO(0x9830)
- #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
- #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
- #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
- 
- #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
- #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
- #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
- 
- #define GDT_CHICKEN_BITS    _MMIO(0x9840)
- #define   GT_NOA_ENABLE	    0x00000080
- 
- #define NOA_DATA	    _MMIO(0x986C)
- #define NOA_WRITE	    _MMIO(0x9888)
- #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
#define _GEN7_PIPEA_DE_LOAD_SL	0x70068
  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
@@@ -1244,177 -249,6 +249,6 @@@
  #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
  #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
- /* See configdb bunit SB addr map */
- #define BUNIT_REG_BISOC				0x11
- 
- /* PUNIT_REG_*SSPM0 */
- #define   _SSPM0_SSC(val)			((val) << 0)
- #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
- #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
- #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
- #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
- #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
- #define   _SSPM0_SSS(val)			((val) << 24)
- #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
- #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
- #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
- #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
- #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
- 
- /* PUNIT_REG_*SSPM1 */
- #define   SSPM1_FREQSTAT_SHIFT			24
- #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
- #define   SSPM1_FREQGUAR_SHIFT			8
- #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
- #define   SSPM1_FREQ_SHIFT			0
- #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
- 
- #define PUNIT_REG_VEDSSPM0			0x32
- #define PUNIT_REG_VEDSSPM1			0x33
- 
- #define PUNIT_REG_DSPSSPM			0x36
- #define   DSPFREQSTAT_SHIFT_CHV			24
- #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
- #define   DSPFREQGUAR_SHIFT_CHV			8
- #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
- #define   DSPFREQSTAT_SHIFT			30
- #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
- #define   DSPFREQGUAR_SHIFT			14
- #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
- #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
- #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
- #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
- #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
- #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
- #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
- #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
- #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
- #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
- #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
- #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
- #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
- #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
- #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
- #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
- 
- #define PUNIT_REG_ISPSSPM0			0x39
- #define PUNIT_REG_ISPSSPM1			0x3a
- 
- #define PUNIT_REG_PWRGT_CTRL			0x60
- #define PUNIT_REG_PWRGT_STATUS			0x61
- #define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
- #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
- #define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
- #define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
- #define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
- 
- #define PUNIT_PWGT_IDX_RENDER			0
- #define PUNIT_PWGT_IDX_MEDIA			1
- #define PUNIT_PWGT_IDX_DISP2D			3
- #define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
- #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
- #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
- #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
- #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
- #define PUNIT_PWGT_IDX_DPIO_RX0			10
- #define PUNIT_PWGT_IDX_DPIO_RX1			11
- #define PUNIT_PWGT_IDX_DPIO_CMN_D		12
- 
- #define PUNIT_REG_GPU_LFM			0xd3
- #define PUNIT_REG_GPU_FREQ_REQ			0xd4
- #define PUNIT_REG_GPU_FREQ_STS			0xd8
- #define   GPLLENABLE				(1 << 4)
- #define   GENFREQSTATUS				(1 << 0)
- #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
- #define PUNIT_REG_CZ_TIMESTAMP			0xce
- 
- #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
- #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
- 
- #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
- #define FB_GFX_FREQ_FUSE_MASK			0xff
- #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
- #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
- #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
- 
- #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
- #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
- 
- #define PUNIT_REG_DDR_SETUP2			0x139
- #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
- #define   FORCE_DDR_LOW_FREQ			(1 << 1)
- #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
- 
- #define PUNIT_GPU_STATUS_REG			0xdb
- #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
- #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
- #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
- #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
- 
- #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
- #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
- #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
- 
- #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
- #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
- #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
- #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
- #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
- #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
- #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
- #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
- #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
- #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
- 
- #define VLV_TURBO_SOC_OVERRIDE		0x04
- #define   VLV_OVERRIDE_EN		1
- #define   VLV_SOC_TDP_EN		(1 << 1)
- #define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
- #define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
- 
- /* vlv2 north clock has */
- #define CCK_FUSE_REG				0x8
- #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
- #define CCK_REG_DSI_PLL_FUSE			0x44
- #define CCK_REG_DSI_PLL_CONTROL			0x48
- #define  DSI_PLL_VCO_EN				(1 << 31)
- #define  DSI_PLL_LDO_GATE			(1 << 30)
- #define  DSI_PLL_P1_POST_DIV_SHIFT		17
- #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
- #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
- #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
- #define  DSI_PLL_MUX_MASK			(3 << 9)
- #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
- #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
- #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
- #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
- #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
- #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
- #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
- #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
- #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
- #define  DSI_PLL_LOCK				(1 << 0)
- #define CCK_REG_DSI_PLL_DIVIDER			0x4c
- #define  DSI_PLL_LFSR				(1 << 31)
- #define  DSI_PLL_FRACTION_EN			(1 << 30)
- #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
- #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
- #define  DSI_PLL_USYNC_CNT_SHIFT		18
- #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
- #define  DSI_PLL_N1_DIV_SHIFT			16
- #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
- #define  DSI_PLL_M1_DIV_SHIFT			0
- #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
- #define CCK_CZ_CLOCK_CONTROL			0x62
- #define CCK_GPLL_CLOCK_CONTROL			0x67
- #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
- #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
- #define  CCK_TRUNK_FORCE_ON			(1 << 17)
- #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
- #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
- #define  CCK_FREQUENCY_STATUS_SHIFT		8
- #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
- 
  /* DPIO registers */
  #define DPIO_DEVFN			0
@@@ -1905,402 -739,6 +739,6 @@@
  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
- /*
-  * ICL Port/COMBO-PHY Registers
-  */
- #define _ICL_COMBOPHY_A			0x162000
- #define _ICL_COMBOPHY_B			0x6C000
- #define _EHL_COMBOPHY_C			0x160000
- #define _RKL_COMBOPHY_D			0x161000
- #define _ADL_COMBOPHY_E			0x16B000
- 
- #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
- 					      _ICL_COMBOPHY_B, \
- 					      _EHL_COMBOPHY_C, \
- 					      _RKL_COMBOPHY_D, \
- 					      _ADL_COMBOPHY_E)
- 
- /* ICL Port CL_DW registers */
- #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 4 * (dw))
- 
- #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
- #define   CL_POWER_DOWN_ENABLE		(1 << 4)
- #define   SUS_CLOCK_CONFIG		(3 << 0)
- 
- #define ICL_PORT_CL_DW10(phy)		_MMIO(_ICL_PORT_CL_DW(10, phy))
- #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
- #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
- #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
- #define  PWR_UP_ALL_LANES		(0x0 << 4)
- #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
- #define  PWR_DOWN_LN_3_2		(0xc << 4)
- #define  PWR_DOWN_LN_3			(0x8 << 4)
- #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
- #define  PWR_DOWN_LN_1_0		(0x3 << 4)
- #define  PWR_DOWN_LN_3_1		(0xa << 4)
- #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
- #define  PWR_DOWN_LN_MASK		(0xf << 4)
- #define  PWR_DOWN_LN_SHIFT		4
- #define  EDP4K2K_MODE_OVRD_EN		(1 << 3)
- #define  EDP4K2K_MODE_OVRD_OPTIMIZED	(1 << 2)
- 
- #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
- #define   ICL_LANE_ENABLE_AUX		(1 << 0)
- 
- /* ICL Port COMP_DW registers */
- #define _ICL_PORT_COMP			0x100
- #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 _ICL_PORT_COMP + 4 * (dw))
- 
- #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
- #define   COMP_INIT			(1 << 31)
- 
- #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
- 
- #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
- #define   PROCESS_INFO_DOT_0		(0 << 26)
- #define   PROCESS_INFO_DOT_1		(1 << 26)
- #define   PROCESS_INFO_DOT_4		(2 << 26)
- #define   PROCESS_INFO_MASK		(7 << 26)
- #define   PROCESS_INFO_SHIFT		26
- #define   VOLTAGE_INFO_0_85V		(0 << 24)
- #define   VOLTAGE_INFO_0_95V		(1 << 24)
- #define   VOLTAGE_INFO_1_05V		(2 << 24)
- #define   VOLTAGE_INFO_MASK		(3 << 24)
- #define   VOLTAGE_INFO_SHIFT		24
- 
- #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
- #define   IREFGEN			(1 << 24)
- 
- #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
- 
- #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
- 
- /* ICL Port PCS registers */
- #define _ICL_PORT_PCS_AUX		0x300
- #define _ICL_PORT_PCS_GRP		0x600
- #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
- #define _ICL_PORT_PCS_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 _ICL_PORT_PCS_AUX + 4 * (dw))
- #define _ICL_PORT_PCS_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 _ICL_PORT_PCS_GRP + 4 * (dw))
- #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
- #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
- #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
- #define ICL_PORT_PCS_DW1_LN(ln, phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
- #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
- #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
- #define   COMMON_KEEPER_EN		(1 << 26)
- #define   LATENCY_OPTIM_MASK		(0x3 << 2)
- #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
- 
- /* ICL Port TX registers */
- #define _ICL_PORT_TX_AUX		0x380
- #define _ICL_PORT_TX_GRP		0x680
- #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
- 
- #define _ICL_PORT_TX_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 _ICL_PORT_TX_AUX + 4 * (dw))
- #define _ICL_PORT_TX_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
- 					 _ICL_PORT_TX_GRP + 4 * (dw))
- #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
- 
- #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
- #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
- #define ICL_PORT_TX_DW2_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
- #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
- #define   SWING_SEL_UPPER_MASK		(1 << 15)
- #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
- #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
- #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
- #define   FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
- #define   RCOMP_SCALAR(x)		((x) << 0)
- #define   RCOMP_SCALAR_MASK		(0xFF << 0)
- 
- #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
- #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
- #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
- #define   LOADGEN_SELECT		(1 << 31)
- #define   POST_CURSOR_1(x)		((x) << 12)
- #define   POST_CURSOR_1_MASK		(0x3F << 12)
- #define   POST_CURSOR_2(x)		((x) << 6)
- #define   POST_CURSOR_2_MASK		(0x3F << 6)
- #define   CURSOR_COEFF(x)		((x) << 0)
- #define   CURSOR_COEFF_MASK		(0x3F << 0)
- 
- #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
- #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
- #define ICL_PORT_TX_DW5_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
- #define   TX_TRAINING_EN		(1 << 31)
- #define   TAP2_DISABLE			(1 << 30)
- #define   TAP3_DISABLE			(1 << 29)
- #define   SCALING_MODE_SEL(x)		((x) << 18)
- #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
- #define   RTERM_SELECT(x)		((x) << 3)
- #define   RTERM_SELECT_MASK		(0x7 << 3)
- 
- #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
- #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
- #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
- #define   N_SCALAR(x)			((x) << 24)
- #define   N_SCALAR_MASK			(0x7F << 24)
- 
- #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
- #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
- #define ICL_PORT_TX_DW8_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
- #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
- #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
- #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
- 
- #define _ICL_DPHY_CHKN_REG			0x194
- #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
- #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
- 
- #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
- 	_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
- 
- #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
- #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
- #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
- #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
- #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
- #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
- #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
- #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
- #define MG_TX1_LINK_PARAMS(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- 				    MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- 				    MG_TX_LINK_PARAMS_TX1LN1_PORT1)
- 
- #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
- #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
- #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
- #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
- #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
- #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
- #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
- #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
- #define MG_TX2_LINK_PARAMS(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- 				    MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- 				    MG_TX_LINK_PARAMS_TX2LN1_PORT1)
- #define   CRI_USE_FS32			(1 << 5)
- 
- #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
- #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
- #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
- #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
- #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
- #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
- #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
- #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
- #define MG_TX1_PISO_READLOAD(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- 				    MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- 				    MG_TX_PISO_READLOAD_TX1LN1_PORT1)
- 
- #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
- #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
- #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
- #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
- #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
- #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
- #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
- #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
- #define MG_TX2_PISO_READLOAD(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- 				    MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- 				    MG_TX_PISO_READLOAD_TX2LN1_PORT1)
- #define   CRI_CALCINIT					(1 << 1)
- 
- #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
- #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
- #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
- #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
- #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
- #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
- #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
- #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
- #define MG_TX1_SWINGCTRL(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- 				    MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- 				    MG_TX_SWINGCTRL_TX1LN1_PORT1)
- 
- #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
- #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
- #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
- #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
- #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
- #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
- #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
- #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
- #define MG_TX2_SWINGCTRL(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- 				    MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- 				    MG_TX_SWINGCTRL_TX2LN1_PORT1)
- #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
- #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
- 
- #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
- #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
- #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
- #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
- #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
- #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
- #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
- #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
- #define MG_TX1_DRVCTRL(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
- 				    MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
- 				    MG_TX_DRVCTRL_TX1LN1_TXPORT1)
- 
- #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
- #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
- #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
- #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
- #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
- #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
- #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
- #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
- #define MG_TX2_DRVCTRL(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
- 				    MG_TX_DRVCTRL_TX2LN0_PORT2, \
- 				    MG_TX_DRVCTRL_TX2LN1_PORT1)
- #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
- #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
- #define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
- #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
- #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
- #define   CRI_LOADGEN_SEL(x)				((x) << 12)
- #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
- 
- #define MG_CLKHUB_LN0_PORT1			0x16839C
- #define MG_CLKHUB_LN1_PORT1			0x16879C
- #define MG_CLKHUB_LN0_PORT2			0x16939C
- #define MG_CLKHUB_LN1_PORT2			0x16979C
- #define MG_CLKHUB_LN0_PORT3			0x16A39C
- #define MG_CLKHUB_LN1_PORT3			0x16A79C
- #define MG_CLKHUB_LN0_PORT4			0x16B39C
- #define MG_CLKHUB_LN1_PORT4			0x16B79C
- #define MG_CLKHUB(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
- 				    MG_CLKHUB_LN0_PORT2, \
- 				    MG_CLKHUB_LN1_PORT1)
- #define   CFG_LOW_RATE_LKREN_EN				(1 << 11)
- 
- #define MG_TX_DCC_TX1LN0_PORT1			0x168110
- #define MG_TX_DCC_TX1LN1_PORT1			0x168510
- #define MG_TX_DCC_TX1LN0_PORT2			0x169110
- #define MG_TX_DCC_TX1LN1_PORT2			0x169510
- #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
- #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
- #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
- #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
- #define MG_TX1_DCC(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
- 				    MG_TX_DCC_TX1LN0_PORT2, \
- 				    MG_TX_DCC_TX1LN1_PORT1)
- #define MG_TX_DCC_TX2LN0_PORT1			0x168090
- #define MG_TX_DCC_TX2LN1_PORT1			0x168490
- #define MG_TX_DCC_TX2LN0_PORT2			0x169090
- #define MG_TX_DCC_TX2LN1_PORT2			0x169490
- #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
- #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
- #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
- #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
- #define MG_TX2_DCC(ln, tc_port) \
- 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
- 				    MG_TX_DCC_TX2LN0_PORT2, \
- 				    MG_TX_DCC_TX2LN1_PORT1)
- #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)	((x) << 25)
- #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
- #define   CFG_AMI_CK_DIV_OVERRIDE_EN		(1 << 24)
- 
- #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
- #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
- #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
- #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
- #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
- #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
- #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
- #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
- #define MG_DP_MODE(ln, tc_port)	\
- 	MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
- 				    MG_DP_MODE_LN0_ACU_PORT2, \
- 				    MG_DP_MODE_LN1_ACU_PORT1)
- #define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
- #define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
- 
- /*
-  * DG2 SNPS PHY registers (TC1 = PHY_E)
-  */
- #define _SNPS_PHY_A_BASE			0x168000
- #define _SNPS_PHY_B_BASE			0x169000
- #define _SNPS_PHY(phy)				_PHY(phy, \
- 						     _SNPS_PHY_A_BASE, \
- 						     _SNPS_PHY_B_BASE)
- #define _SNPS2(phy, reg)			(_SNPS_PHY(phy) - \
- 						 _SNPS_PHY_A_BASE + (reg))
- #define _MMIO_SNPS(phy, reg)			_MMIO(_SNPS2(phy, reg))
- #define _MMIO_SNPS_LN(ln, phy, reg)		_MMIO(_SNPS2(phy, \
- 							     (reg) + (ln) * 0x10))
- 
- #define SNPS_PHY_MPLLB_CP(phy)			_MMIO_SNPS(phy, 0x168000)
- #define   SNPS_PHY_MPLLB_CP_INT			REG_GENMASK(31, 25)
- #define   SNPS_PHY_MPLLB_CP_INT_GS		REG_GENMASK(23, 17)
- #define   SNPS_PHY_MPLLB_CP_PROP		REG_GENMASK(15, 9)
- #define   SNPS_PHY_MPLLB_CP_PROP_GS		REG_GENMASK(7, 1)
- 
- #define SNPS_PHY_MPLLB_DIV(phy)			_MMIO_SNPS(phy, 0x168004)
- #define   SNPS_PHY_MPLLB_FORCE_EN		REG_BIT(31)
- #define   SNPS_PHY_MPLLB_DIV_CLK_EN		REG_BIT(30)
- #define   SNPS_PHY_MPLLB_DIV5_CLK_EN		REG_BIT(29)
- #define   SNPS_PHY_MPLLB_V2I			REG_GENMASK(27, 26)
- #define   SNPS_PHY_MPLLB_FREQ_VCO		REG_GENMASK(25, 24)
- #define   SNPS_PHY_MPLLB_DIV_MULTIPLIER		REG_GENMASK(23, 16)
- #define   SNPS_PHY_MPLLB_PMIX_EN		REG_BIT(10)
- #define   SNPS_PHY_MPLLB_DP2_MODE		REG_BIT(9)
- #define   SNPS_PHY_MPLLB_WORD_DIV2_EN		REG_BIT(8)
- #define   SNPS_PHY_MPLLB_TX_CLK_DIV		REG_GENMASK(7, 5)
- #define   SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL	REG_BIT(0)
- 
- #define SNPS_PHY_MPLLB_FRACN1(phy)		_MMIO_SNPS(phy, 0x168008)
- #define   SNPS_PHY_MPLLB_FRACN_EN		REG_BIT(31)
- #define   SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN	REG_BIT(30)
- #define   SNPS_PHY_MPLLB_FRACN_DEN		REG_GENMASK(15, 0)
- 
- #define SNPS_PHY_MPLLB_FRACN2(phy)		_MMIO_SNPS(phy, 0x16800C)
- #define   SNPS_PHY_MPLLB_FRACN_REM		REG_GENMASK(31, 16)
- #define   SNPS_PHY_MPLLB_FRACN_QUOT		REG_GENMASK(15, 0)
- 
- #define SNPS_PHY_MPLLB_SSCEN(phy)		_MMIO_SNPS(phy, 0x168014)
- #define   SNPS_PHY_MPLLB_SSC_EN			REG_BIT(31)
- #define   SNPS_PHY_MPLLB_SSC_UP_SPREAD		REG_BIT(30)
- #define   SNPS_PHY_MPLLB_SSC_PEAK		REG_GENMASK(29, 10)
- 
- #define SNPS_PHY_MPLLB_SSCSTEP(phy)		_MMIO_SNPS(phy, 0x168018)
- #define   SNPS_PHY_MPLLB_SSC_STEPSIZE		REG_GENMASK(31, 11)
- 
- #define SNPS_PHY_MPLLB_DIV2(phy)		_MMIO_SNPS(phy, 0x16801C)
- #define   SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV	REG_GENMASK(19, 18)
- #define   SNPS_PHY_MPLLB_HDMI_DIV		REG_GENMASK(17, 15)
- #define   SNPS_PHY_MPLLB_REF_CLK_DIV		REG_GENMASK(14, 12)
- #define   SNPS_PHY_MPLLB_MULTIPLIER		REG_GENMASK(11, 0)
- 
- #define SNPS_PHY_REF_CONTROL(phy)		_MMIO_SNPS(phy, 0x168188)
- #define   SNPS_PHY_REF_CONTROL_REF_RANGE	REG_GENMASK(31, 27)
- 
- #define SNPS_PHY_TX_REQ(phy)			_MMIO_SNPS(phy, 0x168200)
- #define   SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR	REG_GENMASK(31, 30)
- 
- #define SNPS_PHY_TX_EQ(ln, phy)			_MMIO_SNPS_LN(ln, phy, 0x168300)
- #define   SNPS_PHY_TX_EQ_MAIN			REG_GENMASK(23, 18)
- #define   SNPS_PHY_TX_EQ_POST			REG_GENMASK(15, 10)
- #define   SNPS_PHY_TX_EQ_PRE			REG_GENMASK(7, 2)
- 
  /* The spec defines this only for BXT PHY0, but lets assume that this
   * would exist for PHY1 too if it had a second channel.
   */
@@@ -2309,21 -747,6 +747,6 @@@
  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
- #define FIA1_BASE			0x163000
- #define FIA2_BASE			0x16E000
- #define FIA3_BASE			0x16F000
- #define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
- #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
- 
- /* ICL PHY DFLEX registers */
- #define PORT_TX_DFLEXDPMLE1(fia)		_MMIO_FIA((fia),  0x008C0)
- #define   DFLEXDPMLE1_DPMLETC_MASK(idx)		(0xf << (4 * (idx)))
- #define   DFLEXDPMLE1_DPMLETC_ML0(idx)		(1 << (4 * (idx)))
- #define   DFLEXDPMLE1_DPMLETC_ML1_0(idx)	(3 << (4 * (idx)))
- #define   DFLEXDPMLE1_DPMLETC_ML3(idx)		(8 << (4 * (idx)))
- #define   DFLEXDPMLE1_DPMLETC_ML3_2(idx)	(12 << (4 * (idx)))
- #define   DFLEXDPMLE1_DPMLETC_ML3_0(idx)	(15 << (4 * (idx)))
- 
  /* BXT PHY Ref registers */
  #define _PORT_REF_DW3_A			0x16218C
  #define _PORT_REF_DW3_BC		0x6C18C
@@@ -2548,65 -971,13 +971,13 @@@
  #define GEN11_VEBOX2_RING_BASE		0x1d8000
  #define XEHP_VEBOX3_RING_BASE		0x1e8000
  #define XEHP_VEBOX4_RING_BASE		0x1f8000
+ #define GEN12_COMPUTE0_RING_BASE	0x1a000
+ #define GEN12_COMPUTE1_RING_BASE	0x1c000
+ #define GEN12_COMPUTE2_RING_BASE	0x1e000
+ #define GEN12_COMPUTE3_RING_BASE	0x26000
  #define BLT_RING_BASE		0x22000
- #define RING_TAIL(base)		_MMIO((base) + 0x30)
- #define RING_HEAD(base)		_MMIO((base) + 0x34)
- #define RING_START(base)	_MMIO((base) + 0x38)
- #define RING_CTL(base)		_MMIO((base) + 0x3c)
- #define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
- #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
- #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
- #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
- #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
- #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
- #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
- #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
- #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
- #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
- #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
- #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
- #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
- #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
- #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
- #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
- #define GEN6_NOSYNC	INVALID_MMIO_REG
- #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
- #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
- #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
- #define RING_ID(base)		_MMIO((base) + 0x8c)
- #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
- 
- #define RING_CMD_CCTL(base)	_MMIO((base) + 0xc4)
- /*
-  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
-  * The lsb of each can be considered a separate enabling bit for encryption.
-  * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
-  * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
-  * 15:14 == Reserved => 31:30 are set to 0.
-  */
- #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
- #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
- #define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
- 			    CMD_CCTL_READ_OVERRIDE_MASK)
- #define CMD_CCTL_MOCS_OVERRIDE(write, read)				      \
- 		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
- 		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
- 
- #define BLIT_CCTL(base) _MMIO((base) + 0x204)
- #define   BLIT_CCTL_DST_MOCS_MASK       REG_GENMASK(14, 8)
- #define   BLIT_CCTL_SRC_MOCS_MASK       REG_GENMASK(6, 0)
- #define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
- 			  BLIT_CCTL_SRC_MOCS_MASK)
- #define   BLIT_CCTL_MOCS(dst, src)				       \
- 		(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
- 		 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
- 
- #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
- #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
- #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
- #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
- 
- #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+ 
+
#define HSW_GTT_CACHE_EN	_MMIO(0x4024)
  #define   GTT_CACHE_EN_ALL	0xF0007FFF
@@@ -2623,190 -994,6 +994,6 @@@
  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
- #define GAMTARBMODE		_MMIO(0x04a08)
- #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
- #define   ARB_MODE_SWIZZLE_BDW	(1 << 1)
- #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
- 
- #define _RING_FAULT_REG_RCS        0x4094
- #define _RING_FAULT_REG_VCS        0x4194
- #define _RING_FAULT_REG_BCS        0x4294
- #define _RING_FAULT_REG_VECS       0x4394
- #define RING_FAULT_REG(engine)     _MMIO(_PICK((engine)->class, \
- 					       _RING_FAULT_REG_RCS, \
- 					       _RING_FAULT_REG_VCS, \
- 					       _RING_FAULT_REG_VECS, \
- 					       _RING_FAULT_REG_BCS))
- #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
- #define GEN12_RING_FAULT_REG	_MMIO(0xcec4)
- #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
- #define   RING_FAULT_GTTSEL_MASK (1 << 11)
- #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
- #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
- #define   RING_FAULT_VALID	(1 << 0)
- #define DONE_REG		_MMIO(0x40b0)
- #define GEN12_GAM_DONE		_MMIO(0xcf68)
- #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
- #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
- #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
- #define GEN12_PAT_INDEX(index)	_MMIO(0x4800 + (index) * 4)
- #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
- #define GEN12_GFX_CCS_AUX_NV	_MMIO(0x4208)
- #define GEN12_VD0_AUX_NV	_MMIO(0x4218)
- #define GEN12_VD1_AUX_NV	_MMIO(0x4228)
- #define GEN12_VD2_AUX_NV	_MMIO(0x4298)
- #define GEN12_VD3_AUX_NV	_MMIO(0x42A8)
- #define GEN12_VE0_AUX_NV	_MMIO(0x4238)
- #define GEN12_VE1_AUX_NV	_MMIO(0x42B8)
- #define   AUX_INV		REG_BIT(0)
- #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
- #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
- #define RING_ACTHD(base)	_MMIO((base) + 0x74)
- #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
- #define RING_NOPID(base)	_MMIO((base) + 0x94)
- #define RING_IMR(base)		_MMIO((base) + 0xa8)
- #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
- #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
- #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
- #define   TAIL_ADDR		0x001FFFF8
- #define   HEAD_WRAP_COUNT	0xFFE00000
- #define   HEAD_WRAP_ONE		0x00200000
- #define   HEAD_ADDR		0x001FFFFC
- #define   RING_NR_PAGES		0x001FF000
- #define   RING_REPORT_MASK	0x00000006
- #define   RING_REPORT_64K	0x00000002
- #define   RING_REPORT_128K	0x00000004
- #define   RING_NO_REPORT	0x00000000
- #define   RING_VALID_MASK	0x00000001
- #define   RING_VALID		0x00000001
- #define   RING_INVALID		0x00000000
- #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
- #define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */
- #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
- 
- #define MISC_STATUS0		_MMIO(0xA500)
- #define MISC_STATUS1		_MMIO(0xA504)
- 
- /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
- #define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)
- #define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)
- 
- #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
- #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)
- #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
- #define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
- #define   RING_FORCE_TO_NONPRIV_ACCESS_WR	(2 << 28)
- #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	(3 << 28)
- #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	(3 << 28)
- #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
- #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
- #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
- #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
- #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
- #define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
- 					(RING_FORCE_TO_NONPRIV_RANGE_MASK \
- 					| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
- #define   RING_MAX_NONPRIV_SLOTS  12
- 
- #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
- 
- #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
- #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1 << 18)
- 
- #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
- #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
- #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
- 
- #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
- #define   GAMT_CHKN_DISABLE_L3_COH_PIPE			(1 << 31)
- #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)
- #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)
- 
- #define GEN8_RTCR	_MMIO(0x4260)
- #define GEN8_M1TCR	_MMIO(0x4264)
- #define GEN8_M2TCR	_MMIO(0x4268)
- #define GEN8_BTCR	_MMIO(0x426c)
- #define GEN8_VTCR	_MMIO(0x4270)
- 
- #if 0
- #define PRB0_TAIL	_MMIO(0x2030)
- #define PRB0_HEAD	_MMIO(0x2034)
- #define PRB0_START	_MMIO(0x2038)
- #define PRB0_CTL	_MMIO(0x203c)
- #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
- #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
- #define PRB1_START	_MMIO(0x2048) /* 915+ only */
- #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
- #endif
- #define IPEIR_I965	_MMIO(0x2064)
- #define IPEHR_I965	_MMIO(0x2068)
- #define GEN7_SC_INSTDONE	_MMIO(0x7100)
- #define GEN12_SC_INSTDONE_EXTRA		_MMIO(0x7104)
- #define GEN12_SC_INSTDONE_EXTRA2	_MMIO(0x7108)
- #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
- #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
- #define XEHPG_INSTDONE_GEOM_SVG		_MMIO(0x666c)
- #define MCFG_MCR_SELECTOR		_MMIO(0xfd0)
- #define SF_MCR_SELECTOR			_MMIO(0xfd8)
- #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
- #define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
- #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
- #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
- #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
- #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
- #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
- #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
- #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
- #define RING_IPEIR(base)	_MMIO((base) + 0x64)
- #define RING_IPEHR(base)	_MMIO((base) + 0x68)
- #define RING_EIR(base)		_MMIO((base) + 0xb0)
- #define RING_EMR(base)		_MMIO((base) + 0xb4)
- #define RING_ESR(base)		_MMIO((base) + 0xb8)
- /*
-  * On GEN4, only the render ring INSTDONE exists and has a different
-  * layout than the GEN7+ version.
-  * The GEN2 counterpart of this register is GEN2_INSTDONE.
-  */
- #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
- #define RING_INSTPS(base)	_MMIO((base) + 0x70)
- #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
- #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
- #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
- #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
- #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
- #define INSTPS		_MMIO(0x2070) /* 965+ only */
- #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
- #define ACTHD_I965	_MMIO(0x2074)
- #define HWS_PGA		_MMIO(0x2080)
- #define HWS_ADDRESS_MASK	0xfffff000
- #define HWS_START_ADDRESS_SHIFT	4
- #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
- #define   PWRCTX_EN	(1 << 0)
- #define IPEIR(base)	_MMIO((base) + 0x88)
- #define IPEHR(base)	_MMIO((base) + 0x8c)
- #define GEN2_INSTDONE	_MMIO(0x2090)
- #define NOPID		_MMIO(0x2094)
- #define HWSTAM		_MMIO(0x2098)
- #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
- #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
- #define   RING_BB_PPGTT		(1 << 5)
- #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
- #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
- #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
- #define RING_BBADDR(base)	_MMIO((base) + 0x140)
- #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
- #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
- #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
- #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
- #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
- 
- #define VDBOX_CGCTL3F10(base)		_MMIO((base) + 0x3f10)
- #define   IECPUNIT_CLKGATE_DIS		REG_BIT(22)
- 
- #define VDBOX_CGCTL3F18(base)		_MMIO((base) + 0x3f18)
- #define   ALNUNIT_CLKGATE_DIS		REG_BIT(13)
- 
- #define ERROR_GEN6	_MMIO(0x40a0)
  #define GEN7_ERR_INT	_MMIO(0x44040)
  #define   ERR_INT_POISON		(1 << 31)
  #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
@@@ -2819,20 -1006,6 +1006,6 @@@
  #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
- #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
- #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
- #define GEN12_FAULT_TLB_DATA0		_MMIO(0xceb8)
- #define GEN12_FAULT_TLB_DATA1		_MMIO(0xcebc)
- #define   FAULT_VA_HIGH_BITS		(0xf << 0)
- #define   FAULT_GTT_SEL			(1 << 4)
- 
- #define GEN12_GFX_TLB_INV_CR	_MMIO(0xced8)
- #define GEN12_VD_TLB_INV_CR	_MMIO(0xcedc)
- #define GEN12_VE_TLB_INV_CR	_MMIO(0xcee0)
- #define GEN12_BLT_TLB_INV_CR	_MMIO(0xcee4)
- 
- #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
- 
  #define FPGA_DBG		_MMIO(0x42300)
  #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
@@@ -2860,95 -1033,6 +1033,6 @@@
  #define   DERRMR_PIPEC_VBLANK		(1 << 21)
  #define   DERRMR_PIPEC_HBLANK		(1 << 22)
- 
- /* GM45+ chicken bits -- debug workaround bits that may be required
-  * for various sorts of correct behavior.  The top 16 bits of each are
-  * the enables for writing to the corresponding low bit.
-  */
- #define _3D_CHICKEN	_MMIO(0x2084)
- #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
- #define _3D_CHICKEN2	_MMIO(0x208c)
- 
- #define FF_SLICE_CHICKEN	_MMIO(0x2088)
- #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX	(1 << 1)
- 
- /* Disables pipelining of read flushes past the SF-WIZ interface.
-  * Required on all Ironlake steppings according to the B-Spec, but the
-  * particular danger of not doing so is not specified.
-  */
- # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
- #define _3D_CHICKEN3	_MMIO(0x2090)
- #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX		(1 << 12)
- #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
- #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
- #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
- #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x) << 1) /* gen8+ */
- #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
- 
- #define MI_MODE		_MMIO(0x209c)
- # define VS_TIMER_DISPATCH				(1 << 6)
- # define MI_FLUSH_ENABLE				(1 << 12)
- # define TGL_NESTED_BB_EN				(1 << 12)
- # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
- # define MODE_IDLE					(1 << 9)
- # define STOP_RING					(1 << 8)
- 
- #define GEN6_GT_MODE	_MMIO(0x20d0)
- #define GEN7_GT_MODE	_MMIO(0x7008)
- #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
- #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
- #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
- #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
- #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
- #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
- #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
- #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
- 
- /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
- #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
- #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
- #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
- 
- #define SCCGCTL94DC		_MMIO(0x94dc)
- #define   CG3DDISURB		REG_BIT(14)
- 
- #define MLTICTXCTL		_MMIO(0xb170)
- #define   TDONRENDER		REG_BIT(2)
- 
- #define L3SQCREG1_CCS0		_MMIO(0xb200)
- #define   FLUSHALLNONCOH	REG_BIT(5)
- 
- /* WaClearTdlStateAckDirtyBits */
- #define GEN8_STATE_ACK		_MMIO(0x20F0)
- #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
- #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
- #define   GEN9_STATE_ACK_TDL0 (1 << 12)
- #define   GEN9_STATE_ACK_TDL1 (1 << 13)
- #define   GEN9_STATE_ACK_TDL2 (1 << 14)
- #define   GEN9_STATE_ACK_TDL3 (1 << 15)
- #define   GEN9_SUBSLICE_TDL_ACK_BITS \
- 	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
- 	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
- 
- #define GFX_MODE	_MMIO(0x2520)
- #define GFX_MODE_GEN7	_MMIO(0x229c)
- #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
- #define   GFX_RUN_LIST_ENABLE		(1 << 15)
- #define   GFX_INTERRUPT_STEERING	(1 << 14)
- #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
- #define   GFX_SURFACE_FAULT_ENABLE	(1 << 12)
- #define   GFX_REPLAY_MODE		(1 << 11)
- #define   GFX_PSMI_GRANULARITY		(1 << 10)
- #define   GFX_PPGTT_ENABLE		(1 << 9)
- #define   GEN8_GFX_PPGTT_48B		(1 << 7)
- 
- #define   GFX_FORWARD_VBLANK_MASK	(3 << 5)
- #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
- #define   GFX_FORWARD_VBLANK_ALWAYS	(1 << 5)
- #define   GFX_FORWARD_VBLANK_COND	(2 << 5)
- 
- #define   GEN11_GFX_DISABLE_LEGACY_MODE	(1 << 3)
- 
  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
  #define SCPD0		_MMIO(0x209c) /* 915+ only */
@@@ -2988,7 -1072,6 +1072,6 @@@
  #define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
  #define   INSTPM_TLB_INVALIDATE	(1 << 9)
  #define   INSTPM_SYNC_FLUSH	(1 << 5)
- #define ACTHD(base)	_MMIO((base) + 0xc8)
  #define MEM_MODE	_MMIO(0x20cc)
  #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
  #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@@ -3115,132 -1198,6 +1198,6 @@@
  #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
  #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
- #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
- #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
- #define   CM0_IZ_OPT_DISABLE      (1 << 6)
- #define   CM0_ZR_OPT_DISABLE      (1 << 5)
- #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1 << 5)
- #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
- #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
- #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
- #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
- #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
- #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
- #define   GFX_FLSH_CNTL_EN	(1 << 0)
- #define ECOSKPD		_MMIO(0x21d0)
- #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
- #define   ECO_GATING_CX_ONLY	(1 << 3)
- #define   ECO_FLIP_DONE		(1 << 0)
- 
- #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
- #define RC_OP_FLUSH_ENABLE (1 << 0)
- #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
- #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
- #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)
- #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
- #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
- 
- #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
- #define   GEN6_BLITTER_LOCK_SHIFT			16
- #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
- 
- #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
- #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
- #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
- #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
- #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)
- 
- #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
- #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
- 
- #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
- #define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
- #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	REG_BIT(4)
- 
- /* Fuse readout registers for GT */
- #define HSW_PAVP_FUSE1			_MMIO(0x911C)
- #define   XEHP_SFC_ENABLE_MASK		REG_GENMASK(27, 24)
- #define   HSW_F1_EU_DIS_MASK		REG_GENMASK(17, 16)
- #define   HSW_F1_EU_DIS_10EUS		0
- #define   HSW_F1_EU_DIS_8EUS		1
- #define   HSW_F1_EU_DIS_6EUS		2
- 
- #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
- #define   CHV_FGT_DISABLE_SS0		(1 << 10)
- #define   CHV_FGT_DISABLE_SS1		(1 << 11)
- #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
- #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
- #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
- #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
- #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
- #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
- #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
- #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
- 
- #define GEN8_FUSE2			_MMIO(0x9120)
- #define   GEN8_F2_SS_DIS_SHIFT		21
- #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
- #define   GEN8_F2_S_ENA_SHIFT		25
- #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
- 
- #define   GEN9_F2_SS_DIS_SHIFT		20
- #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
- 
- #define   GEN10_F2_S_ENA_SHIFT		22
- #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
- #define   GEN10_F2_SS_DIS_SHIFT		18
- #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
- 
- #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
- #define GEN10_L3BANK_PAIR_COUNT     4
- #define GEN10_L3BANK_MASK   0x0F
- /* on Xe_HP the same fuses indicates mslices instead of L3 banks */
- #define GEN12_MAX_MSLICES 4
- #define GEN12_MEML3_EN_MASK 0x0F
- 
- #define GEN8_EU_DISABLE0		_MMIO(0x9134)
- #define   GEN8_EU_DIS0_S0_MASK		0xffffff
- #define   GEN8_EU_DIS0_S1_SHIFT		24
- #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
- 
- #define GEN8_EU_DISABLE1		_MMIO(0x9138)
- #define   GEN8_EU_DIS1_S1_MASK		0xffff
- #define   GEN8_EU_DIS1_S2_SHIFT		16
- #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
- 
- #define GEN8_EU_DISABLE2		_MMIO(0x913c)
- #define   GEN8_EU_DIS2_S2_MASK		0xff
- 
- #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
- 
- #define GEN10_EU_DISABLE3		_MMIO(0x9140)
- #define   GEN10_EU_DIS_SS_MASK		0xff
- 
- #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
- #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
- #define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
- #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
- 
- #define GEN11_EU_DISABLE _MMIO(0x9134)
- #define GEN11_EU_DIS_MASK 0xFF
- 
- #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
- #define GEN11_GT_S_ENA_MASK 0xFF
- 
- #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
- 
- #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913C)
- #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
- 
- #define XEHP_EU_ENABLE			_MMIO(0x9134)
- #define XEHP_EU_ENA_MASK		0xFF
- 
- #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
- #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
- #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
- #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
- #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
- 
  /* On modern GEN architectures interrupt control consists of two sets
   * of registers. The first set pertains to the ring generating the
   * interrupt. The second control is for the functional block generating the
@@@ -3398,10 -1355,10 +1355,10 @@@
  #define FBC_LL_SIZE		(1536)
/* Framebuffer compression for GM45+ */
- #define DPFC_CB_BASE		_MMIO(0x3200)
- #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
- #define DPFC_CONTROL		_MMIO(0x3208)
- #define ILK_DPFC_CONTROL	_MMIO(0x43208)
+ #define DPFC_CB_BASE			_MMIO(0x3200)
+ #define ILK_DPFC_CB_BASE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+ #define DPFC_CONTROL			_MMIO(0x3208)
+ #define ILK_DPFC_CONTROL(fbc_id)	_MMIO_PIPE((fbc_id), 0x43208, 0x43248)
  #define   DPFC_CTL_EN				REG_BIT(31)
  #define   DPFC_CTL_PLANE_MASK_G4X		REG_BIT(30) /* g4x-snb */
  #define   DPFC_CTL_PLANE_G4X(i9xx_plane)	REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
@@@ -3419,28 -1376,28 +1376,28 @@@
  #define   DPFC_CTL_LIMIT_4X			REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
  #define   DPFC_CTL_FENCENO_MASK			REG_GENMASK(3, 0)
  #define   DPFC_CTL_FENCENO(fence)		REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
- #define DPFC_RECOMP_CTL		_MMIO(0x320c)
- #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
+ #define DPFC_RECOMP_CTL			_MMIO(0x320c)
+ #define ILK_DPFC_RECOMP_CTL(fbc_id)	_MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
  #define   DPFC_RECOMP_STALL_EN			REG_BIT(27)
  #define   DPFC_RECOMP_STALL_WM_MASK		REG_GENMASK(26, 16)
  #define   DPFC_RECOMP_TIMER_COUNT_MASK		REG_GENMASK(5, 0)
- #define DPFC_STATUS		_MMIO(0x3210)
- #define ILK_DPFC_STATUS		_MMIO(0x43210)
+ #define DPFC_STATUS			_MMIO(0x3210)
+ #define ILK_DPFC_STATUS(fbc_id)		_MMIO_PIPE((fbc_id), 0x43210, 0x43250)
  #define   DPFC_INVAL_SEG_MASK			REG_GENMASK(26, 16)
  #define   DPFC_COMP_SEG_MASK			REG_GENMASK(10, 0)
- #define DPFC_STATUS2		_MMIO(0x3214)
- #define ILK_DPFC_STATUS2		_MMIO(0x43214)
+ #define DPFC_STATUS2			_MMIO(0x3214)
+ #define ILK_DPFC_STATUS2(fbc_id)	_MMIO_PIPE((fbc_id), 0x43214, 0x43254)
  #define   DPFC_COMP_SEG_MASK_IVB		REG_GENMASK(11, 0)
- #define DPFC_FENCE_YOFF		_MMIO(0x3218)
- #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
- #define DPFC_CHICKEN		_MMIO(0x3224)
- #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
+ #define DPFC_FENCE_YOFF			_MMIO(0x3218)
+ #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+ #define DPFC_CHICKEN			_MMIO(0x3224)
+ #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
  #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
  #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
  #define   DPFC_CHICKEN_COMP_DUMMY_PIXEL		REG_BIT(14) /* glk+ */
  #define   DPFC_DISABLE_DUMMY0			REG_BIT(8) /* ivb+ */
- #define GLK_FBC_STRIDE		_MMIO(0x43228)
+ #define GLK_FBC_STRIDE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43228, 0x43268)
  #define   FBC_STRIDE_OVERRIDE	REG_BIT(15)
  #define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
  #define   FBC_STRIDE(x)		REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
@@@ -3483,9 -1440,9 +1440,9 @@@
  #define IPS_CTL		_MMIO(0x43408)
  #define   IPS_ENABLE	(1 << 31)
- #define MSG_FBC_REND_STATE	_MMIO(0x50380)
+ #define MSG_FBC_REND_STATE(fbc_id)	_MMIO_PIPE((fbc_id), 0x50380, 0x50384)
  #define   FBC_REND_NUKE			REG_BIT(2)
- #define   FBC_REND_CACHE_CLEAN			REG_BIT(1)
+ #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
/*
   * GPIO regs
@@@ -3874,413 -1831,12 +1831,12 @@@
    				    _PALETTE_B, _CHV_PALETTE_C) + \
    			      (i) * 4)
- /* MCH MMIO space */
- 
- /*
-  * MCHBAR mirror.
-  *
-  * This mirrors the MCHBAR MMIO space whose location is determined by
-  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
-  * every way.  It is not accessible from the CP register read instructions.
-  *
-  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
-  * just read.
-  */
- #define MCHBAR_MIRROR_BASE	0x10000
- 
- #define MCHBAR_MIRROR_BASE_SNB	0x140000
- 
- #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
- #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
- #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
- #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
- #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
- 
- /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
- #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
- 
- /* 915-945 and GM965 MCH register controlling DRAM channel access */
- #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
- #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
- #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
- #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
- #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
- #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
- #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
- #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
- #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
- 
- /* Pineview MCH register contains DDR3 setting */
- #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
- #define CSHRDDR3CTL_DDR3       (1 << 2)
- 
- /* 965 MCH register controlling DRAM channel configuration */
- #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
- #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
- 
- /* snb MCH registers for reading the DRAM channel configuration */
- #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
- #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
- #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
- #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
- #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
- #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
- #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
- #define   MAD_DIMM_ECC_ON		(0x3 << 24)
- #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
- #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
- #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
- #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
- #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
- #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
- #define   MAD_DIMM_A_SELECT		(0x1 << 16)
- /* DIMM sizes are in multiples of 256mb. */
- #define   MAD_DIMM_B_SIZE_SHIFT		8
- #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
- #define   MAD_DIMM_A_SIZE_SHIFT		0
- #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
- 
- /* snb MCH registers for priority tuning */
- #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
- #define   MCH_SSKPD_WM0_MASK		0x3f
- #define   MCH_SSKPD_WM0_VAL		0xc
- 
- /* Clocking configuration register */
- #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
- #define CLKCFG_FSB_400					(0 << 0)	/* hrawclk 100 */
- #define CLKCFG_FSB_400_ALT				(5 << 0)	/* hrawclk 100 */
- #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
- #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
- #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
- #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
- #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
- #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
- #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
- #define CLKCFG_FSB_1600_ALT				(6 << 0)	/* hrawclk 400 */
- #define CLKCFG_FSB_MASK					(7 << 0)
- #define CLKCFG_MEM_533					(1 << 4)
- #define CLKCFG_MEM_667					(2 << 4)
- #define CLKCFG_MEM_800					(3 << 4)
- #define CLKCFG_MEM_MASK					(7 << 4)
- 
- #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
- #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
- 
- #define TSC1			_MMIO(0x11001)
- #define   TSE			(1 << 0)
- #define TR1			_MMIO(0x11006)
- #define TSFS			_MMIO(0x11020)
- #define   TSFS_SLOPE_MASK	0x0000ff00
- #define   TSFS_SLOPE_SHIFT	8
- #define   TSFS_INTR_MASK	0x000000ff
- 
- #define CRSTANDVID		_MMIO(0x11100)
- #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
- #define   PXVFREQ_PX_MASK	0x7f000000
- #define   PXVFREQ_PX_SHIFT	24
- #define VIDFREQ_BASE		_MMIO(0x11110)
- #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
- #define VIDFREQ2		_MMIO(0x11114)
- #define VIDFREQ3		_MMIO(0x11118)
- #define VIDFREQ4		_MMIO(0x1111c)
- #define   VIDFREQ_P0_MASK	0x1f000000
- #define   VIDFREQ_P0_SHIFT	24
- #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
- #define   VIDFREQ_P0_CSCLK_SHIFT 20
- #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
- #define   VIDFREQ_P0_CRCLK_SHIFT 16
- #define   VIDFREQ_P1_MASK	0x00001f00
- #define   VIDFREQ_P1_SHIFT	8
- #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
- #define   VIDFREQ_P1_CSCLK_SHIFT 4
- #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
- #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
- #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
- #define   INTTOEXT_MAP3_SHIFT	24
- #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
- #define   INTTOEXT_MAP2_SHIFT	16
- #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
- #define   INTTOEXT_MAP1_SHIFT	8
- #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
- #define   INTTOEXT_MAP0_SHIFT	0
- #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
- #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
- #define   MEMCTL_CMD_MASK	0xe000
- #define   MEMCTL_CMD_SHIFT	13
- #define   MEMCTL_CMD_RCLK_OFF	0
- #define   MEMCTL_CMD_RCLK_ON	1
- #define   MEMCTL_CMD_CHFREQ	2
- #define   MEMCTL_CMD_CHVID	3
- #define   MEMCTL_CMD_VMMOFF	4
- #define   MEMCTL_CMD_VMMON	5
- #define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
- 					   when command complete */
- #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
- #define   MEMCTL_FREQ_SHIFT	8
- #define   MEMCTL_SFCAVM		(1 << 7)
- #define   MEMCTL_TGT_VID_MASK	0x007f
- #define MEMIHYST		_MMIO(0x1117c)
- #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
- #define   MEMINT_RSEXIT_EN	(1 << 8)
- #define   MEMINT_CX_SUPR_EN	(1 << 7)
- #define   MEMINT_CONT_BUSY_EN	(1 << 6)
- #define   MEMINT_AVG_BUSY_EN	(1 << 5)
- #define   MEMINT_EVAL_CHG_EN	(1 << 4)
- #define   MEMINT_MON_IDLE_EN	(1 << 3)
- #define   MEMINT_UP_EVAL_EN	(1 << 2)
- #define   MEMINT_DOWN_EVAL_EN	(1 << 1)
- #define   MEMINT_SW_CMD_EN	(1 << 0)
- #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
- #define   MEM_RSEXIT_MASK	0xc000
- #define   MEM_RSEXIT_SHIFT	14
- #define   MEM_CONT_BUSY_MASK	0x3000
- #define   MEM_CONT_BUSY_SHIFT	12
- #define   MEM_AVG_BUSY_MASK	0x0c00
- #define   MEM_AVG_BUSY_SHIFT	10
- #define   MEM_EVAL_CHG_MASK	0x0300
- #define   MEM_EVAL_BUSY_SHIFT	8
- #define   MEM_MON_IDLE_MASK	0x00c0
- #define   MEM_MON_IDLE_SHIFT	6
- #define   MEM_UP_EVAL_MASK	0x0030
- #define   MEM_UP_EVAL_SHIFT	4
- #define   MEM_DOWN_EVAL_MASK	0x000c
- #define   MEM_DOWN_EVAL_SHIFT	2
- #define   MEM_SW_CMD_MASK	0x0003
- #define   MEM_INT_STEER_GFX	0
- #define   MEM_INT_STEER_CMR	1
- #define   MEM_INT_STEER_SMI	2
- #define   MEM_INT_STEER_SCI	3
- #define MEMINTRSTS		_MMIO(0x11184)
- #define   MEMINT_RSEXIT		(1 << 7)
- #define   MEMINT_CONT_BUSY	(1 << 6)
- #define   MEMINT_AVG_BUSY	(1 << 5)
- #define   MEMINT_EVAL_CHG	(1 << 4)
- #define   MEMINT_MON_IDLE	(1 << 3)
- #define   MEMINT_UP_EVAL	(1 << 2)
- #define   MEMINT_DOWN_EVAL	(1 << 1)
- #define   MEMINT_SW_CMD		(1 << 0)
- #define MEMMODECTL		_MMIO(0x11190)
- #define   MEMMODE_BOOST_EN	(1 << 31)
- #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
- #define   MEMMODE_BOOST_FREQ_SHIFT 24
- #define   MEMMODE_IDLE_MODE_MASK 0x00030000
- #define   MEMMODE_IDLE_MODE_SHIFT 16
- #define   MEMMODE_IDLE_MODE_EVAL 0
- #define   MEMMODE_IDLE_MODE_CONT 1
- #define   MEMMODE_HWIDLE_EN	(1 << 15)
- #define   MEMMODE_SWMODE_EN	(1 << 14)
- #define   MEMMODE_RCLK_GATE	(1 << 13)
- #define   MEMMODE_HW_UPDATE	(1 << 12)
- #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
- #define   MEMMODE_FSTART_SHIFT	8
- #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
- #define   MEMMODE_FMAX_SHIFT	4
- #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
- #define RCBMAXAVG		_MMIO(0x1119c)
- #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
- #define   SWMEMCMD_RENDER_OFF	(0 << 13)
- #define   SWMEMCMD_RENDER_ON	(1 << 13)
- #define   SWMEMCMD_SWFREQ	(2 << 13)
- #define   SWMEMCMD_TARVID	(3 << 13)
- #define   SWMEMCMD_VRM_OFF	(4 << 13)
- #define   SWMEMCMD_VRM_ON	(5 << 13)
- #define   CMDSTS		(1 << 12)
- #define   SFCAVM		(1 << 11)
- #define   SWFREQ_MASK		0x0380 /* P0-7 */
- #define   SWFREQ_SHIFT		7
- #define   TARVID_MASK		0x001f
- #define MEMSTAT_CTG		_MMIO(0x111a0)
- #define RCBMINAVG		_MMIO(0x111a0)
- #define RCUPEI			_MMIO(0x111b0)
- #define RCDNEI			_MMIO(0x111b4)
- #define RSTDBYCTL		_MMIO(0x111b8)
- #define   RS1EN			(1 << 31)
- #define   RS2EN			(1 << 30)
- #define   RS3EN			(1 << 29)
- #define   D3RS3EN		(1 << 28) /* Display D3 imlies RS3 */
- #define   SWPROMORSX		(1 << 27) /* RSx promotion timers ignored */
- #define   RCWAKERW		(1 << 26) /* Resetwarn from PCH causes wakeup */
- #define   DPRSLPVREN		(1 << 25) /* Fast voltage ramp enable */
- #define   GFXTGHYST		(1 << 24) /* Hysteresis to allow trunk gating */
- #define   RCX_SW_EXIT		(1 << 23) /* Leave RSx and prevent re-entry */
- #define   RSX_STATUS_MASK	(7 << 20)
- #define   RSX_STATUS_ON		(0 << 20)
- #define   RSX_STATUS_RC1	(1 << 20)
- #define   RSX_STATUS_RC1E	(2 << 20)
- #define   RSX_STATUS_RS1	(3 << 20)
- #define   RSX_STATUS_RS2	(4 << 20) /* aka rc6 */
- #define   RSX_STATUS_RSVD	(5 << 20) /* deep rc6 unsupported on ilk */
- #define   RSX_STATUS_RS3	(6 << 20) /* rs3 unsupported on ilk */
- #define   RSX_STATUS_RSVD2	(7 << 20)
- #define   UWRCRSXE		(1 << 19) /* wake counter limit prevents rsx */
- #define   RSCRP			(1 << 18) /* rs requests control on rs1/2 reqs */
- #define   JRSC			(1 << 17) /* rsx coupled to cpu c-state */
- #define   RS2INC0		(1 << 16) /* allow rs2 in cpu c0 */
- #define   RS1CONTSAV_MASK	(3 << 14)
- #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
- #define   RS1CONTSAV_RSVD	(1 << 14)
- #define   RS1CONTSAV_SAVE_RS1	(2 << 14) /* rs1 saves context */
- #define   RS1CONTSAV_FULL_RS1	(3 << 14) /* rs1 saves and restores context */
- #define   NORMSLEXLAT_MASK	(3 << 12)
- #define   SLOW_RS123		(0 << 12)
- #define   SLOW_RS23		(1 << 12)
- #define   SLOW_RS3		(2 << 12)
- #define   NORMAL_RS123		(3 << 12)
- #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
- #define   IMPROMOEN		(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
- #define   RCENTSYNC		(1 << 9) /* rs coupled to cpu c-state (3/6/7) */
- #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
- #define   RS_CSTATE_MASK	(3 << 4)
- #define   RS_CSTATE_C367_RS1	(0 << 4)
- #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
- #define   RS_CSTATE_RSVD	(2 << 4)
- #define   RS_CSTATE_C367_RS2	(3 << 4)
- #define   REDSAVES		(1 << 3) /* no context save if was idle during rs0 */
- #define   REDRESTORES		(1 << 2) /* no restore if was idle during rs0 */
- #define VIDCTL			_MMIO(0x111c0)
- #define VIDSTS			_MMIO(0x111c8)
- #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
- #define MEMSTAT_ILK		_MMIO(0x111f8)
- #define   MEMSTAT_VID_MASK	0x7f00
- #define   MEMSTAT_VID_SHIFT	8
- #define   MEMSTAT_PSTATE_MASK	0x00f8
- #define   MEMSTAT_PSTATE_SHIFT  3
- #define   MEMSTAT_MON_ACTV	(1 << 2)
- #define   MEMSTAT_SRC_CTL_MASK	0x0003
- #define   MEMSTAT_SRC_CTL_CORE	0
- #define   MEMSTAT_SRC_CTL_TRB	1
- #define   MEMSTAT_SRC_CTL_THM	2
- #define   MEMSTAT_SRC_CTL_STDBY 3
- #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
- #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
- #define PMMISC			_MMIO(0x11214)
- #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
- #define SDEW			_MMIO(0x1124c)
- #define CSIEW0			_MMIO(0x11250)
- #define CSIEW1			_MMIO(0x11254)
- #define CSIEW2			_MMIO(0x11258)
- #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
- #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
- #define MCHAFE			_MMIO(0x112c0)
- #define CSIEC			_MMIO(0x112e0)
- #define DMIEC			_MMIO(0x112e4)
- #define DDREC			_MMIO(0x112e8)
- #define PEG0EC			_MMIO(0x112ec)
- #define PEG1EC			_MMIO(0x112f0)
- #define GFXEC			_MMIO(0x112f4)
- #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
- #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
- #define ECR			_MMIO(0x11600)
- #define   ECR_GPFE		(1 << 31)
- #define   ECR_IMONE		(1 << 30)
- #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
- #define OGW0			_MMIO(0x11608)
- #define OGW1			_MMIO(0x1160c)
- #define EG0			_MMIO(0x11610)
- #define EG1			_MMIO(0x11614)
- #define EG2			_MMIO(0x11618)
- #define EG3			_MMIO(0x1161c)
- #define EG4			_MMIO(0x11620)
- #define EG5			_MMIO(0x11624)
- #define EG6			_MMIO(0x11628)
- #define EG7			_MMIO(0x1162c)
- #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
- #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
- #define LCFUSE02		_MMIO(0x116c0)
- #define   LCFUSE_HIV_MASK	0x000000ff
- #define CSIPLL0			_MMIO(0x12c10)
- #define DDRMPLL1		_MMIO(0X12c20)
  #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
- #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
- #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
- 
- #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
- #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
- #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
- #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
- #define   RP0_CAP_MASK		REG_GENMASK(7, 0)
- #define   RP1_CAP_MASK		REG_GENMASK(15, 8)
- #define   RPN_CAP_MASK		REG_GENMASK(23, 16)
  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
  #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
  #define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)
- /*
-  * Logical Context regs
-  */
- #define CCID(base)			_MMIO((base) + 0x180)
- #define   CCID_EN			BIT(0)
- #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
- #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
- /*
-  * Notes on SNB/IVB/VLV context size:
-  * - Power context is saved elsewhere (LLC or stolen)
-  * - Ring/execlist context is saved on SNB, not on IVB
-  * - Extended context size already includes render context size
-  * - We always need to follow the extended context size.
-  *   SNB BSpec has comments indicating that we should use the
-  *   render context size instead if execlists are disabled, but
-  *   based on empirical testing that's just nonsense.
-  * - Pipelined/VF state is saved on SNB/IVB respectively
-  * - GT1 size just indicates how much of render context
-  *   doesn't need saving on GT1
-  */
- #define CXT_SIZE		_MMIO(0x21a0)
- #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
- #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
- #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
- #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
- #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
- #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
- 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
- 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
- #define GEN7_CXT_SIZE		_MMIO(0x21a8)
- #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
- #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
- #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
- #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
- #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
- #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
- #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
- 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
- 
- enum {
- 	INTEL_ADVANCED_CONTEXT = 0,
- 	INTEL_LEGACY_32B_CONTEXT,
- 	INTEL_ADVANCED_AD_CONTEXT,
- 	INTEL_LEGACY_64B_CONTEXT
- };
- 
- enum {
- 	FAULT_AND_HANG = 0,
- 	FAULT_AND_HALT, /* Debug only */
- 	FAULT_AND_STREAM,
- 	FAULT_AND_CONTINUE /* Unsupported */
- };
- 
- #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
- #define GEN8_CTX_VALID (1 << 0)
- #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
- #define GEN8_CTX_FORCE_RESTORE (1 << 2)
- #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
- #define GEN8_CTX_PRIVILEGE (1 << 8)
- #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
- 
- #define GEN8_CTX_ID_SHIFT 32
- #define GEN8_CTX_ID_WIDTH 21
- #define GEN11_SW_CTX_ID_SHIFT 37
- #define GEN11_SW_CTX_ID_WIDTH 11
- #define GEN11_ENGINE_CLASS_SHIFT 61
- #define GEN11_ENGINE_CLASS_WIDTH 3
- #define GEN11_ENGINE_INSTANCE_SHIFT 48
- #define GEN11_ENGINE_INSTANCE_WIDTH 6
- 
- #define XEHP_SW_CTX_ID_SHIFT 39
- #define XEHP_SW_CTX_ID_WIDTH 16
- #define XEHP_SW_COUNTER_SHIFT 58
- #define XEHP_SW_COUNTER_WIDTH 6
- 
  #define CHV_CLK_CTL1			_MMIO(0x101100)
  #define VLV_CLK_CTL2			_MMIO(0x101104)
  #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
@@@ -4331,75 -1887,6 +1887,6 @@@
  #define CLKGATE_DIS_PSL(pipe) \
    _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
- /*
-  * GEN10 clock gating regs
-  */
- 
- #define UNSLCGCTL9440			_MMIO(0x9440)
- #define   GAMTLBOACS_CLKGATE_DIS	REG_BIT(28)
- #define   GAMTLBVDBOX5_CLKGATE_DIS	REG_BIT(27)
- #define   GAMTLBVDBOX6_CLKGATE_DIS	REG_BIT(26)
- #define   GAMTLBVDBOX3_CLKGATE_DIS	REG_BIT(24)
- #define   GAMTLBVDBOX4_CLKGATE_DIS	REG_BIT(23)
- #define   GAMTLBVDBOX7_CLKGATE_DIS	REG_BIT(22)
- #define   GAMTLBVDBOX2_CLKGATE_DIS	REG_BIT(21)
- #define   GAMTLBVDBOX0_CLKGATE_DIS	REG_BIT(17)
- #define   GAMTLBKCR_CLKGATE_DIS		REG_BIT(16)
- #define   GAMTLBGUC_CLKGATE_DIS		REG_BIT(15)
- #define   GAMTLBBLT_CLKGATE_DIS		REG_BIT(14)
- #define   GAMTLBVDBOX1_CLKGATE_DIS	REG_BIT(6)
- 
- #define UNSLCGCTL9444			_MMIO(0x9444)
- #define   GAMTLBGFXA0_CLKGATE_DIS	REG_BIT(30)
- #define   GAMTLBGFXA1_CLKGATE_DIS	REG_BIT(29)
- #define   GAMTLBCOMPA0_CLKGATE_DIS	REG_BIT(28)
- #define   GAMTLBCOMPA1_CLKGATE_DIS	REG_BIT(27)
- #define   GAMTLBCOMPB0_CLKGATE_DIS	REG_BIT(26)
- #define   GAMTLBCOMPB1_CLKGATE_DIS	REG_BIT(25)
- #define   GAMTLBCOMPC0_CLKGATE_DIS	REG_BIT(24)
- #define   GAMTLBCOMPC1_CLKGATE_DIS	REG_BIT(23)
- #define   GAMTLBCOMPD0_CLKGATE_DIS	REG_BIT(22)
- #define   GAMTLBCOMPD1_CLKGATE_DIS	REG_BIT(21)
- #define   GAMTLBMERT_CLKGATE_DIS	REG_BIT(20)
- #define   GAMTLBVEBOX3_CLKGATE_DIS	REG_BIT(19)
- #define   GAMTLBVEBOX2_CLKGATE_DIS	REG_BIT(18)
- #define   GAMTLBVEBOX1_CLKGATE_DIS	REG_BIT(17)
- #define   GAMTLBVEBOX0_CLKGATE_DIS	REG_BIT(16)
- #define   LTCDD_CLKGATE_DIS		REG_BIT(10)
- 
- #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
- #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
- #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
- #define  MSCUNIT_CLKGATE_DIS		(1 << 10)
- #define  NODEDSS_CLKGATE_DIS		REG_BIT(12)
- #define  L3_CLKGATE_DIS			REG_BIT(16)
- #define  L3_CR2X_CLKGATE_DIS		REG_BIT(17)
- 
- #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
- #define   DSS_ROUTER_CLKGATE_DIS	REG_BIT(28)
- #define   GWUNIT_CLKGATE_DIS		REG_BIT(16)
- 
- #define SUBSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x9528)
- #define  CPSSUNIT_CLKGATE_DIS		REG_BIT(9)
- 
- #define SSMCGCTL9530			_MMIO(0x9530)
- #define   RTFUNIT_CLKGATE_DIS		REG_BIT(18)
- 
- #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
- #define   VFUNIT_CLKGATE_DIS		REG_BIT(20)
- #define   TSGUNIT_CLKGATE_DIS		REG_BIT(17) /* XEHPSDV */
- #define   CG3DDISCFEG_CLKGATE_DIS	REG_BIT(17) /* DG2 */
- #define   GAMEDIA_CLKGATE_DIS		REG_BIT(11)
- #define   HSUNIT_CLKGATE_DIS		REG_BIT(8)
- #define   VSUNIT_CLKGATE_DIS		REG_BIT(3)
- 
- #define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
- #define   VSUNIT_CLKGATE_DIS_TGL	REG_BIT(19)
- #define   PSDUNIT_CLKGATE_DIS		REG_BIT(5)
- 
- #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
- #define   CGPSF_CLKGATE_DIS		(1 << 3)
- 
  /*
   * Display engine regs
   */
@@@ -4494,6 -1981,10 +1981,10 @@@
  #define _VSYNC_A	0x60014
  #define _EXITLINE_A	0x60018
  #define _PIPEASRC	0x6001c
+ #define   PIPESRC_WIDTH_MASK	REG_GENMASK(31, 16)
+ #define   PIPESRC_WIDTH(w)	REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+ #define   PIPESRC_HEIGHT_MASK	REG_GENMASK(15, 0)
+ #define   PIPESRC_HEIGHT(h)	REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
  #define _BCLRPAT_A	0x60020
  #define _VSYNCSHIFT_A	0x60028
  #define _PIPE_MULT_A	0x6002c
@@@ -4829,7 -2320,6 +2320,7 @@@
  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
 +#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(31)
  #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
  #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
@@@ -6145,16 -3635,14 +3636,14 @@@
  #define _PIPEB_DATA_M_G4X	0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
- #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
- #define  TU_SIZE_SHIFT		25
- #define  TU_SIZE_MASK           (0x3f << 25)
+ #define  TU_SIZE_MASK		REG_GENMASK(30, 25)
+ #define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
- #define  DATA_LINK_M_N_MASK	(0xffffff)
+ #define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
  #define  DATA_LINK_N_MAX	(0x800000)
#define _PIPEA_DATA_N_G4X	0x70054
  #define _PIPEB_DATA_N_G4X	0x71054
- #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
/*
   * Computing Link M and N values for the Display Port link
@@@ -6169,11 -3657,8 +3658,8 @@@
#define _PIPEA_LINK_M_G4X	0x70060
  #define _PIPEB_LINK_M_G4X	0x71060
- #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
- 
  #define _PIPEA_LINK_N_G4X	0x70064
  #define _PIPEB_LINK_N_G4X	0x71064
- #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
  #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
@@@ -6184,65 -3669,61 +3670,61 @@@
/* Pipe A */
  #define _PIPEADSL		0x70000
- #define   DSL_LINEMASK_GEN2	0x00000fff
- #define   DSL_LINEMASK_GEN3	0x00001fff
+ #define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */
+ #define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
  #define _PIPEACONF		0x70008
- #define   PIPECONF_ENABLE	(1 << 31)
- #define   PIPECONF_DISABLE	0
- #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
- #define   I965_PIPECONF_ACTIVE	(1 << 30)
- #define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
- #define   PIPECONF_FRAME_START_DELAY_MASK	(3 << 27) /* pre-hsw */
- #define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
- #define   PIPECONF_SINGLE_WIDE	0
- #define   PIPECONF_PIPE_UNLOCKED 0
- #define   PIPECONF_PIPE_LOCKED	(1 << 25)
- #define   PIPECONF_FORCE_BORDER	(1 << 25)
- #define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
- #define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
- #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
- #define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
- #define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
- #define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
- #define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
- #define   PIPECONF_GAMMA_MODE_SHIFT	24
- #define   PIPECONF_INTERLACE_MASK	(7 << 21)
- #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
- /* Note that pre-gen3 does not support interlaced display directly. Panel
-  * fitting must be disabled on pre-ilk for interlaced. */
- #define   PIPECONF_PROGRESSIVE			(0 << 21)
- #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
- #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
- #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
- #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
- /* Ironlake and later have a complete new set of values for interlaced. PFIT
-  * means panel fitter required, PF means progressive fetch, DBL means power
-  * saving pixel doubling. */
- #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
- #define   PIPECONF_INTERLACED_ILK		(3 << 21)
- #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
- #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
- #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
- #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
- #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
- #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
- #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
- #define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
- #define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
- #define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
- #define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
- #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
- #define   PIPECONF_BPC_MASK	(0x7 << 5)
- #define   PIPECONF_8BPC		(0 << 5)
- #define   PIPECONF_10BPC	(1 << 5)
- #define   PIPECONF_6BPC		(2 << 5)
- #define   PIPECONF_12BPC	(3 << 5)
- #define   PIPECONF_DITHER_EN	(1 << 4)
- #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
- #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
- #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
- #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
- #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
+ #define   PIPECONF_ENABLE			REG_BIT(31)
+ #define   PIPECONF_DOUBLE_WIDE			REG_BIT(30) /* pre-i965 */
+ #define   PIPECONF_STATE_ENABLE			REG_BIT(30) /* i965+ */
+ #define   PIPECONF_DSI_PLL_LOCKED		REG_BIT(29) /* vlv & pipe A only */
+ #define   PIPECONF_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* pre-hsw */
+ #define   PIPECONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+ #define   PIPECONF_PIPE_LOCKED			REG_BIT(25)
+ #define   PIPECONF_FORCE_BORDER			REG_BIT(25)
+ #define   PIPECONF_GAMMA_MODE_MASK_I9XX		REG_BIT(24) /* gmch */
+ #define   PIPECONF_GAMMA_MODE_MASK_ILK		REG_GENMASK(25, 24) /* ilk-ivb */
+ #define   PIPECONF_GAMMA_MODE_8BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
+ #define   PIPECONF_GAMMA_MODE_10BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
+ #define   PIPECONF_GAMMA_MODE_12BIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
+ #define   PIPECONF_GAMMA_MODE_SPLIT		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
+ #define   PIPECONF_GAMMA_MODE(x)		REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
+ #define   PIPECONF_INTERLACE_MASK		REG_GENMASK(23, 21) /* gen3+ */
+ #define   PIPECONF_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
+ #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
+ #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
+ #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
+ #define   PIPECONF_INTERLACE_FIELD_0_ONLY	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
+ /*
+  * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
+  * DBL=power saving pixel doubling, PF-ID* requires panel fitter
+  */
+ #define   PIPECONF_INTERLACE_MASK_ILK		REG_GENMASK(23, 21) /* ilk+ */
+ #define   PIPECONF_INTERLACE_MASK_HSW		REG_GENMASK(22, 21) /* hsw+ */
+ #define   PIPECONF_INTERLACE_PF_PD_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
+ #define   PIPECONF_INTERLACE_PF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
+ #define   PIPECONF_INTERLACE_IF_ID_ILK		REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
+ #define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
+ #define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
+ #define   PIPECONF_EDP_RR_MODE_SWITCH		REG_BIT(20)
+ #define   PIPECONF_CXSR_DOWNCLOCK		REG_BIT(16)
+ #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	REG_BIT(14)
+ #define   PIPECONF_COLOR_RANGE_SELECT		REG_BIT(13)
+ #define   PIPECONF_OUTPUT_COLORSPACE_MASK	REG_GENMASK(12, 11) /* ilk-ivb */
+ #define   PIPECONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
+ #define   PIPECONF_OUTPUT_COLORSPACE_YUV601	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
+ #define   PIPECONF_OUTPUT_COLORSPACE_YUV709	REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
+ #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	REG_BIT(11) /* hsw only */
+ #define   PIPECONF_BPC_MASK			REG_GENMASK(7, 5) /* ctg-ivb */
+ #define   PIPECONF_BPC_8			REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
+ #define   PIPECONF_BPC_10			REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
+ #define   PIPECONF_BPC_6			REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
+ #define   PIPECONF_BPC_12			REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
+ #define   PIPECONF_DITHER_EN			REG_BIT(4)
+ #define   PIPECONF_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
+ #define   PIPECONF_DITHER_TYPE_SP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
+ #define   PIPECONF_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
+ #define   PIPECONF_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
+ #define   PIPECONF_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
  #define _PIPEASTAT		0x70024
  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
@@@ -6327,38 -3808,41 +3809,41 @@@
#define _PIPE_MISC_A			0x70030
  #define _PIPE_MISC_B			0x71030
- #define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
- #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
- #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
- #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
- #define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
+ #define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */
+ #define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */
+ #define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
+ #define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)
+ #define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */
  /*
   * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
   * valid values of: 6, 8, 10 BPC.
   * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
   * 6, 8, 10, 12 BPC.
   */
- #define   PIPEMISC_BPC_MASK		(7 << 5)
- #define   PIPEMISC_8_BPC		(0 << 5)
- #define   PIPEMISC_10_BPC		(1 << 5)
- #define   PIPEMISC_6_BPC		(2 << 5)
- #define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
- #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
- #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
- #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
+ #define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)
+ #define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
+ #define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
+ #define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
+ #define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
+ #define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)
+ #define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)
+ #define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
+ #define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
+ #define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
+ #define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
#define _PIPE_MISC2_A					0x7002C
  #define _PIPE_MISC2_B					0x7102C
- #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
- #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
- #define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
+ #define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)
+ #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
+ #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
  #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
/* Skylake+ pipe bottom (background) color */
  #define _SKL_BOTTOM_COLOR_A		0x70034
- #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
- #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
+ #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE		REG_BIT(31)
+ #define   SKL_BOTTOM_COLOR_CSC_ENABLE		REG_BIT(30)
  #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
#define _ICL_PIPE_A_STATUS			0x70058
@@@ -6699,49 -4183,32 +4184,32 @@@
  #define _WM0_PIPEC_IVB		0x45200
  #define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
    				    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
- #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
- #define  WM0_PIPE_PLANE_SHIFT	16
- #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
- #define  WM0_PIPE_SPRITE_SHIFT	8
- #define  WM0_PIPE_CURSOR_MASK	(0xff)
+ #define  WM0_PIPE_PRIMARY_MASK	REG_GENMASK(31, 16)
+ #define  WM0_PIPE_SPRITE_MASK	REG_GENMASK(15, 8)
+ #define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(7, 0)
+ #define  WM0_PIPE_PRIMARY(x)	REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
+ #define  WM0_PIPE_SPRITE(x)	REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
+ #define  WM0_PIPE_CURSOR(x)	REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
  #define WM1_LP_ILK		_MMIO(0x45108)
- #define  WM1_LP_SR_EN		(1 << 31)
- #define  WM1_LP_LATENCY_SHIFT	24
- #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
- #define  WM1_LP_FBC_MASK	(0xf << 20)
- #define  WM1_LP_FBC_SHIFT	20
- #define  WM1_LP_FBC_SHIFT_BDW	19
- #define  WM1_LP_SR_MASK		(0x7ff << 8)
- #define  WM1_LP_SR_SHIFT	8
- #define  WM1_LP_CURSOR_MASK	(0xff)
  #define WM2_LP_ILK		_MMIO(0x4510c)
- #define  WM2_LP_EN		(1 << 31)
  #define WM3_LP_ILK		_MMIO(0x45110)
- #define  WM3_LP_EN		(1 << 31)
+ #define  WM_LP_ENABLE		REG_BIT(31)
+ #define  WM_LP_LATENCY_MASK	REG_GENMASK(30, 24)
+ #define  WM_LP_FBC_MASK_BDW	REG_GENMASK(23, 19)
+ #define  WM_LP_FBC_MASK_ILK	REG_GENMASK(23, 20)
+ #define  WM_LP_PRIMARY_MASK	REG_GENMASK(18, 8)
+ #define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
+ #define  WM_LP_LATENCY(x)	REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
+ #define  WM_LP_FBC_BDW(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
+ #define  WM_LP_FBC_ILK(x)	REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
+ #define  WM_LP_PRIMARY(x)	REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
+ #define  WM_LP_CURSOR(x)	REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
  #define WM1S_LP_ILK		_MMIO(0x45120)
  #define WM2S_LP_IVB		_MMIO(0x45124)
  #define WM3S_LP_IVB		_MMIO(0x45128)
- #define  WM1S_LP_EN		(1 << 31)
- 
- #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
- 	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
- 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
- 
- /* Memory latency timer register */
- #define MLTR_ILK		_MMIO(0x11222)
- #define  MLTR_WM1_SHIFT		0
- #define  MLTR_WM2_SHIFT		8
- /* the unit of memory self-refresh latency time is 0.5us */
- #define  ILK_SRLT_MASK		0x3f
- 
- 
- /* the address where we get all kinds of latency value */
- #define SSKPD			_MMIO(0x5d10)
- #define SSKPD_WM_MASK		0x3f
- #define SSKPD_WM0_SHIFT		0
- #define SSKPD_WM1_SHIFT		8
- #define SSKPD_WM2_SHIFT		16
- #define SSKPD_WM3_SHIFT		24
+ #define  WM_LP_SPRITE_ENABLE	REG_BIT(31) /* ilk/snb WM1S only */
+ #define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
+ #define  WM_LP_SPRITE(x)	REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
/*
   * The two pipe frame counter registers are not synchronized, so
@@@ -6775,44 -4242,50 +4243,50 @@@
  /* Cursor A & B regs */
  #define _CURACNTR		0x70080
  /* Old style CUR*CNTR flags (desktop 8xx) */
- #define   CURSOR_ENABLE		0x80000000
- #define   CURSOR_GAMMA_ENABLE	0x40000000
- #define   CURSOR_STRIDE_SHIFT	28
- #define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
- #define   CURSOR_FORMAT_SHIFT	24
- #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
- #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
- #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
- #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
- #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
- #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
+ #define   CURSOR_ENABLE			REG_BIT(31)
+ #define   CURSOR_PIPE_GAMMA_ENABLE	REG_BIT(30)
+ #define   CURSOR_STRIDE_MASK	REG_GENMASK(29, 28)
+ #define   CURSOR_STRIDE(stride)	REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
+ #define   CURSOR_FORMAT_MASK	REG_GENMASK(26, 24)
+ #define   CURSOR_FORMAT_2C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
+ #define   CURSOR_FORMAT_3C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
+ #define   CURSOR_FORMAT_4C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
+ #define   CURSOR_FORMAT_ARGB	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
+ #define   CURSOR_FORMAT_XRGB	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
  /* New style CUR*CNTR flags */
- #define   MCURSOR_MODE		0x27
- #define   MCURSOR_MODE_DISABLE   0x00
- #define   MCURSOR_MODE_128_32B_AX 0x02
- #define   MCURSOR_MODE_256_32B_AX 0x03
- #define   MCURSOR_MODE_64_32B_AX 0x07
- #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
- #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
- #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
  #define   MCURSOR_ARB_SLOTS_MASK	REG_GENMASK(30, 28) /* icl+ */
  #define   MCURSOR_ARB_SLOTS(x)		REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
- #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
- #define   MCURSOR_PIPE_SELECT_SHIFT	28
- #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
- #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
- #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
- #define   MCURSOR_ROTATE_180	(1 << 15)
- #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
+ #define   MCURSOR_PIPE_SEL_MASK		REG_GENMASK(29, 28)
+ #define   MCURSOR_PIPE_SEL(pipe)	REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
+ #define   MCURSOR_PIPE_GAMMA_ENABLE	REG_BIT(26)
+ #define   MCURSOR_PIPE_CSC_ENABLE	REG_BIT(24) /* ilk+ */
+ #define   MCURSOR_ROTATE_180		REG_BIT(15)
+ #define   MCURSOR_TRICKLE_FEED_DISABLE	REG_BIT(14)
+ #define   MCURSOR_MODE_MASK		0x27
+ #define   MCURSOR_MODE_DISABLE		0x00
+ #define   MCURSOR_MODE_128_32B_AX	0x02
+ #define   MCURSOR_MODE_256_32B_AX	0x03
+ #define   MCURSOR_MODE_64_32B_AX	0x07
+ #define   MCURSOR_MODE_128_ARGB_AX	(0x20 | MCURSOR_MODE_128_32B_AX)
+ #define   MCURSOR_MODE_256_ARGB_AX	(0x20 | MCURSOR_MODE_256_32B_AX)
+ #define   MCURSOR_MODE_64_ARGB_AX	(0x20 | MCURSOR_MODE_64_32B_AX)
  #define _CURABASE		0x70084
  #define _CURAPOS		0x70088
- #define   CURSOR_POS_MASK       0x007FF
- #define   CURSOR_POS_SIGN       0x8000
- #define   CURSOR_X_SHIFT        0
- #define   CURSOR_Y_SHIFT        16
- #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
+ #define   CURSOR_POS_Y_SIGN		REG_BIT(31)
+ #define   CURSOR_POS_Y_MASK		REG_GENMASK(30, 16)
+ #define   CURSOR_POS_Y(y)		REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
+ #define   CURSOR_POS_X_SIGN		REG_BIT(15)
+ #define   CURSOR_POS_X_MASK		REG_GENMASK(14, 0)
+ #define   CURSOR_POS_X(x)		REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+ #define _CURASIZE		0x700a0 /* 845/865 */
+ #define   CURSOR_HEIGHT_MASK		REG_GENMASK(21, 12)
+ #define   CURSOR_HEIGHT(h)		REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
+ #define   CURSOR_WIDTH_MASK		REG_GENMASK(9, 0)
+ #define   CURSOR_WIDTH(w)		REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
  #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
- #define   CUR_FBC_CTL_EN	(1 << 31)
+ #define   CUR_FBC_EN			REG_BIT(31)
+ #define   CUR_FBC_HEIGHT_MASK		REG_GENMASK(7, 0)
+ #define   CUR_FBC_HEIGHT(h)		REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
  #define _CURASURFLIVE		0x700ac /* g4x+ */
  #define _CURBCNTR		0x700c0
  #define _CURBBASE		0x700c4
@@@ -6825,6 -4298,7 +4299,7 @@@
  #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
  #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
  #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
+ #define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
  #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
  #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
@@@ -6838,49 -4312,54 +4313,54 @@@
  /* Display A control */
  #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
  #define _DSPACNTR				0x70180
- #define   DISPLAY_PLANE_ENABLE			(1 << 31)
- #define   DISPLAY_PLANE_DISABLE			0
- #define   DISPPLANE_GAMMA_ENABLE		(1 << 30)
- #define   DISPPLANE_GAMMA_DISABLE		0
- #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
- #define   DISPPLANE_YUV422			(0x0 << 26)
- #define   DISPPLANE_8BPP			(0x2 << 26)
- #define   DISPPLANE_BGRA555			(0x3 << 26)
- #define   DISPPLANE_BGRX555			(0x4 << 26)
- #define   DISPPLANE_BGRX565			(0x5 << 26)
- #define   DISPPLANE_BGRX888			(0x6 << 26)
- #define   DISPPLANE_BGRA888			(0x7 << 26)
- #define   DISPPLANE_RGBX101010			(0x8 << 26)
- #define   DISPPLANE_RGBA101010			(0x9 << 26)
- #define   DISPPLANE_BGRX101010			(0xa << 26)
- #define   DISPPLANE_BGRA101010			(0xb << 26)
- #define   DISPPLANE_RGBX161616			(0xc << 26)
- #define   DISPPLANE_RGBX888			(0xe << 26)
- #define   DISPPLANE_RGBA888			(0xf << 26)
- #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
- #define   DISPPLANE_STEREO_DISABLE		0
- #define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
- #define   DISPPLANE_SEL_PIPE_SHIFT		24
- #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
- #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
- #define   DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
- #define   DISPPLANE_SRC_KEY_DISABLE		0
- #define   DISPPLANE_LINE_DOUBLE			(1 << 20)
- #define   DISPPLANE_NO_LINE_DOUBLE		0
- #define   DISPPLANE_STEREO_POLARITY_FIRST	0
- #define   DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
- #define   DISPPLANE_ALPHA_PREMULTIPLY		(1 << 16) /* CHV pipe B */
- #define   DISPPLANE_ROTATE_180			(1 << 15)
- #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1 << 14) /* Ironlake */
- #define   DISPPLANE_TILED			(1 << 10)
- #define   DISPPLANE_ASYNC_FLIP			(1 << 9) /* g4x+ */
- #define   DISPPLANE_MIRROR			(1 << 8) /* CHV pipe B */
+ #define   DISP_ENABLE			REG_BIT(31)
+ #define   DISP_PIPE_GAMMA_ENABLE	REG_BIT(30)
+ #define   DISP_FORMAT_MASK		REG_GENMASK(29, 26)
+ #define   DISP_FORMAT_8BPP		REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+ #define   DISP_FORMAT_BGRA555		REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+ #define   DISP_FORMAT_BGRX555		REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+ #define   DISP_FORMAT_BGRX565		REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+ #define   DISP_FORMAT_BGRX888		REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+ #define   DISP_FORMAT_BGRA888		REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+ #define   DISP_FORMAT_RGBX101010	REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+ #define   DISP_FORMAT_RGBA101010	REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+ #define   DISP_FORMAT_BGRX101010	REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+ #define   DISP_FORMAT_BGRA101010	REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+ #define   DISP_FORMAT_RGBX161616	REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+ #define   DISP_FORMAT_RGBX888		REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+ #define   DISP_FORMAT_RGBA888		REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+ #define   DISP_STEREO_ENABLE		REG_BIT(25)
+ #define   DISP_PIPE_CSC_ENABLE		REG_BIT(24) /* ilk+ */
+ #define   DISP_PIPE_SEL_MASK		REG_GENMASK(25, 24)
+ #define   DISP_PIPE_SEL(pipe)		REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
+ #define   DISP_SRC_KEY_ENABLE		REG_BIT(22)
+ #define   DISP_LINE_DOUBLE		REG_BIT(20)
+ #define   DISP_STEREO_POLARITY_SECOND	REG_BIT(18)
+ #define   DISP_ALPHA_PREMULTIPLY	REG_BIT(16) /* CHV pipe B */
+ #define   DISP_ROTATE_180		REG_BIT(15)
+ #define   DISP_TRICKLE_FEED_DISABLE	REG_BIT(14) /* g4x+ */
+ #define   DISP_TILED			REG_BIT(10)
+ #define   DISP_ASYNC_FLIP		REG_BIT(9) /* g4x+ */
+ #define   DISP_MIRROR			REG_BIT(8) /* CHV pipe B */
  #define _DSPAADDR				0x70184
  #define _DSPASTRIDE				0x70188
  #define _DSPAPOS				0x7018C /* reserved */
+ #define   DISP_POS_Y_MASK		REG_GENMASK(31, 0)
+ #define   DISP_POS_Y(y)			REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
+ #define   DISP_POS_X_MASK		REG_GENMASK(15, 0)
+ #define   DISP_POS_X(x)			REG_FIELD_PREP(DISP_POS_X_MASK, (x))
  #define _DSPASIZE				0x70190
+ #define   DISP_HEIGHT_MASK		REG_GENMASK(31, 0)
+ #define   DISP_HEIGHT(h)		REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+ #define   DISP_WIDTH_MASK		REG_GENMASK(15, 0)
+ #define   DISP_WIDTH(w)			REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
  #define _DSPASURF				0x7019C /* 965+ only */
+ #define   DISP_ADDR_MASK		REG_GENMASK(31, 12)
  #define _DSPATILEOFF				0x701A4 /* 965+ only */
+ #define   DISP_OFFSET_Y_MASK		REG_GENMASK(31, 16)
+ #define   DISP_OFFSET_Y(y)		REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
+ #define   DISP_OFFSET_X_MASK		REG_GENMASK(15, 0)
+ #define   DISP_OFFSET_X(x)		REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
  #define _DSPAOFFSET				0x701A4 /* HSW */
  #define _DSPASURFLIVE				0x701AC
  #define _DSPAGAMC				0x701E0
@@@ -6900,15 -4379,28 +4380,28 @@@
/* CHV pipe B blender and primary plane */
  #define _CHV_BLEND_A		0x60a00
- #define   CHV_BLEND_LEGACY		(0 << 30)
- #define   CHV_BLEND_ANDROID		(1 << 30)
- #define   CHV_BLEND_MPO			(2 << 30)
- #define   CHV_BLEND_MASK		(3 << 30)
+ #define   CHV_BLEND_MASK	REG_GENMASK(31, 30)
+ #define   CHV_BLEND_LEGACY	REG_FIELD_PREP(CHV_BLEND_MASK, 0)
+ #define   CHV_BLEND_ANDROID	REG_FIELD_PREP(CHV_BLEND_MASK, 1)
+ #define   CHV_BLEND_MPO		REG_FIELD_PREP(CHV_BLEND_MASK, 2)
  #define _CHV_CANVAS_A		0x60a04
+ #define   CHV_CANVAS_RED_MASK	REG_GENMASK(29, 20)
+ #define   CHV_CANVAS_GREEN_MASK	REG_GENMASK(19, 10)
+ #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
  #define _PRIMPOS_A		0x60a08
+ #define   PRIM_POS_Y_MASK	REG_GENMASK(31, 16)
+ #define   PRIM_POS_Y(y)		REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+ #define   PRIM_POS_X_MASK	REG_GENMASK(15, 0)
+ #define   PRIM_POS_X(x)		REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
  #define _PRIMSIZE_A		0x60a0c
+ #define   PRIM_HEIGHT_MASK	REG_GENMASK(31, 16)
+ #define   PRIM_HEIGHT(h)	REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+ #define   PRIM_WIDTH_MASK	REG_GENMASK(15, 0)
+ #define   PRIM_WIDTH(w)		REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
  #define _PRIMCNSTALPHA_A	0x60a10
- #define   PRIM_CONST_ALPHA_ENABLE	(1 << 31)
+ #define   PRIM_CONST_ALPHA_ENABLE	REG_BIT(31)
+ #define   PRIM_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
+ #define   PRIM_CONST_ALPHA(alpha)	REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
#define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
  #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
@@@ -6949,10 -4441,8 +4442,8 @@@
/* Display B control */
  #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
- #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
- #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
- #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
- #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
+ #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
+ #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
  #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
  #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
  #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
@@@ -6968,46 -4458,63 +4459,63 @@@
/* Sprite A control */
  #define _DVSACNTR		0x72180
- #define   DVS_ENABLE		(1 << 31)
- #define   DVS_GAMMA_ENABLE	(1 << 30)
- #define   DVS_YUV_RANGE_CORRECTION_DISABLE	(1 << 27)
- #define   DVS_PIXFORMAT_MASK	(3 << 25)
- #define   DVS_FORMAT_YUV422	(0 << 25)
- #define   DVS_FORMAT_RGBX101010	(1 << 25)
- #define   DVS_FORMAT_RGBX888	(2 << 25)
- #define   DVS_FORMAT_RGBX161616	(3 << 25)
- #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
- #define   DVS_SOURCE_KEY	(1 << 22)
- #define   DVS_RGB_ORDER_XBGR	(1 << 20)
- #define   DVS_YUV_FORMAT_BT709	(1 << 18)
- #define   DVS_YUV_ORDER_MASK	(3 << 16)
- #define   DVS_YUV_ORDER_YUYV	(0 << 16)
- #define   DVS_YUV_ORDER_UYVY	(1 << 16)
- #define   DVS_YUV_ORDER_YVYU	(2 << 16)
- #define   DVS_YUV_ORDER_VYUY	(3 << 16)
- #define   DVS_ROTATE_180	(1 << 15)
- #define   DVS_DEST_KEY		(1 << 2)
- #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
- #define   DVS_TILED		(1 << 10)
+ #define   DVS_ENABLE			REG_BIT(31)
+ #define   DVS_PIPE_GAMMA_ENABLE		REG_BIT(30)
+ #define   DVS_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(27)
+ #define   DVS_FORMAT_MASK		REG_GENMASK(26, 25)
+ #define   DVS_FORMAT_YUV422		REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+ #define   DVS_FORMAT_RGBX101010		REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
+ #define   DVS_FORMAT_RGBX888		REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+ #define   DVS_FORMAT_RGBX161616		REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
+ #define   DVS_PIPE_CSC_ENABLE		REG_BIT(24)
+ #define   DVS_SOURCE_KEY		REG_BIT(22)
+ #define   DVS_RGB_ORDER_XBGR		REG_BIT(20)
+ #define   DVS_YUV_FORMAT_BT709		REG_BIT(18)
+ #define   DVS_YUV_ORDER_MASK		REG_GENMASK(17, 16)
+ #define   DVS_YUV_ORDER_YUYV		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+ #define   DVS_YUV_ORDER_UYVY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+ #define   DVS_YUV_ORDER_YVYU		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+ #define   DVS_YUV_ORDER_VYUY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+ #define   DVS_ROTATE_180		REG_BIT(15)
+ #define   DVS_TRICKLE_FEED_DISABLE	REG_BIT(14)
+ #define   DVS_TILED			REG_BIT(10)
+ #define   DVS_DEST_KEY			REG_BIT(2)
  #define _DVSALINOFF		0x72184
  #define _DVSASTRIDE		0x72188
  #define _DVSAPOS		0x7218c
+ #define   DVS_POS_Y_MASK		REG_GENMASK(31, 16)
+ #define   DVS_POS_Y(y)			REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+ #define   DVS_POS_X_MASK		REG_GENMASK(15, 0)
+ #define   DVS_POS_X(x)			REG_FIELD_PREP(DVS_POS_X_MASK, (x))
  #define _DVSASIZE		0x72190
+ #define   DVS_HEIGHT_MASK		REG_GENMASK(31, 16)
+ #define   DVS_HEIGHT(h)			REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
+ #define   DVS_WIDTH_MASK		REG_GENMASK(15, 0)
+ #define   DVS_WIDTH(w)			REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
  #define _DVSAKEYVAL		0x72194
  #define _DVSAKEYMSK		0x72198
  #define _DVSASURF		0x7219c
+ #define   DVS_ADDR_MASK			REG_GENMASK(31, 12)
  #define _DVSAKEYMAXVAL		0x721a0
  #define _DVSATILEOFF		0x721a4
+ #define   DVS_OFFSET_Y_MASK		REG_GENMASK(31, 16)
+ #define   DVS_OFFSET_Y(y)		REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+ #define   DVS_OFFSET_X_MASK		REG_GENMASK(15, 0)
+ #define   DVS_OFFSET_X(x)		REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
  #define _DVSASURFLIVE		0x721ac
  #define _DVSAGAMC_G4X		0x721e0 /* g4x */
  #define _DVSASCALE		0x72204
- #define   DVS_SCALE_ENABLE	(1 << 31)
- #define   DVS_FILTER_MASK	(3 << 29)
- #define   DVS_FILTER_MEDIUM	(0 << 29)
- #define   DVS_FILTER_ENHANCING	(1 << 29)
- #define   DVS_FILTER_SOFTENING	(2 << 29)
- #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
- #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
+ #define   DVS_SCALE_ENABLE		REG_BIT(31)
+ #define   DVS_FILTER_MASK		REG_GENMASK(30, 29)
+ #define   DVS_FILTER_MEDIUM		REG_FIELD_PREP(DVS_FILTER_MASK, 0)
+ #define   DVS_FILTER_ENHANCING		REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+ #define   DVS_FILTER_SOFTENING		REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+ #define   DVS_VERTICAL_OFFSET_HALF	REG_BIT(28) /* must be enabled below */
+ #define   DVS_VERTICAL_OFFSET_ENABLE	REG_BIT(27)
+ #define   DVS_SRC_WIDTH_MASK		REG_GENMASK(26, 16)
+ #define   DVS_SRC_WIDTH(w)		REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
+ #define   DVS_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
+ #define   DVS_SRC_HEIGHT(h)		REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
  #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
  #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
@@@ -7044,50 -4551,67 +4552,67 @@@
  #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
#define _SPRA_CTL		0x70280
- #define   SPRITE_ENABLE			(1 << 31)
- #define   SPRITE_GAMMA_ENABLE		(1 << 30)
- #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
- #define   SPRITE_PIXFORMAT_MASK		(7 << 25)
- #define   SPRITE_FORMAT_YUV422		(0 << 25)
- #define   SPRITE_FORMAT_RGBX101010	(1 << 25)
- #define   SPRITE_FORMAT_RGBX888		(2 << 25)
- #define   SPRITE_FORMAT_RGBX161616	(3 << 25)
- #define   SPRITE_FORMAT_YUV444		(4 << 25)
- #define   SPRITE_FORMAT_XR_BGR101010	(5 << 25) /* Extended range */
- #define   SPRITE_PIPE_CSC_ENABLE	(1 << 24)
- #define   SPRITE_SOURCE_KEY		(1 << 22)
- #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
- #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
- #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
- #define   SPRITE_YUV_ORDER_MASK		(3 << 16)
- #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
- #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
- #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
- #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
- #define   SPRITE_ROTATE_180		(1 << 15)
- #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
- #define   SPRITE_INT_GAMMA_DISABLE	(1 << 13)
- #define   SPRITE_TILED			(1 << 10)
- #define   SPRITE_DEST_KEY		(1 << 2)
+ #define   SPRITE_ENABLE				REG_BIT(31)
+ #define   SPRITE_PIPE_GAMMA_ENABLE		REG_BIT(30)
+ #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(28)
+ #define   SPRITE_FORMAT_MASK			REG_GENMASK(27, 25)
+ #define   SPRITE_FORMAT_YUV422			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
+ #define   SPRITE_FORMAT_RGBX101010		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
+ #define   SPRITE_FORMAT_RGBX888			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
+ #define   SPRITE_FORMAT_RGBX161616		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
+ #define   SPRITE_FORMAT_YUV444			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
+ #define   SPRITE_FORMAT_XR_BGR101010		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
+ #define   SPRITE_PIPE_CSC_ENABLE		REG_BIT(24)
+ #define   SPRITE_SOURCE_KEY			REG_BIT(22)
+ #define   SPRITE_RGB_ORDER_RGBX			REG_BIT(20) /* only for 888 and 161616 */
+ #define   SPRITE_YUV_TO_RGB_CSC_DISABLE		REG_BIT(19)
+ #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	REG_BIT(18) /* 0 is BT601 */
+ #define   SPRITE_YUV_ORDER_MASK			REG_GENMASK(17, 16)
+ #define   SPRITE_YUV_ORDER_YUYV			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
+ #define   SPRITE_YUV_ORDER_UYVY			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
+ #define   SPRITE_YUV_ORDER_YVYU			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
+ #define   SPRITE_YUV_ORDER_VYUY			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
+ #define   SPRITE_ROTATE_180			REG_BIT(15)
+ #define   SPRITE_TRICKLE_FEED_DISABLE		REG_BIT(14)
+ #define   SPRITE_PLANE_GAMMA_DISABLE		REG_BIT(13)
+ #define   SPRITE_TILED				REG_BIT(10)
+ #define   SPRITE_DEST_KEY			REG_BIT(2)
  #define _SPRA_LINOFF		0x70284
  #define _SPRA_STRIDE		0x70288
  #define _SPRA_POS		0x7028c
+ #define   SPRITE_POS_Y_MASK	REG_GENMASK(31, 16)
+ #define   SPRITE_POS_Y(y)	REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
+ #define   SPRITE_POS_X_MASK	REG_GENMASK(15, 0)
+ #define   SPRITE_POS_X(x)	REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
  #define _SPRA_SIZE		0x70290
+ #define   SPRITE_HEIGHT_MASK	REG_GENMASK(31, 16)
+ #define   SPRITE_HEIGHT(h)	REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
+ #define   SPRITE_WIDTH_MASK	REG_GENMASK(15, 0)
+ #define   SPRITE_WIDTH(w)	REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
  #define _SPRA_KEYVAL		0x70294
  #define _SPRA_KEYMSK		0x70298
  #define _SPRA_SURF		0x7029c
+ #define   SPRITE_ADDR_MASK	REG_GENMASK(31, 12)
  #define _SPRA_KEYMAX		0x702a0
  #define _SPRA_TILEOFF		0x702a4
+ #define   SPRITE_OFFSET_Y_MASK	REG_GENMASK(31, 16)
+ #define   SPRITE_OFFSET_Y(y)	REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
+ #define   SPRITE_OFFSET_X_MASK	REG_GENMASK(15, 0)
+ #define   SPRITE_OFFSET_X(x)	REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
  #define _SPRA_OFFSET		0x702a4
  #define _SPRA_SURFLIVE		0x702ac
  #define _SPRA_SCALE		0x70304
- #define   SPRITE_SCALE_ENABLE	(1 << 31)
- #define   SPRITE_FILTER_MASK	(3 << 29)
- #define   SPRITE_FILTER_MEDIUM	(0 << 29)
- #define   SPRITE_FILTER_ENHANCING	(1 << 29)
- #define   SPRITE_FILTER_SOFTENING	(2 << 29)
- #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
- #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
+ #define   SPRITE_SCALE_ENABLE			REG_BIT(31)
+ #define   SPRITE_FILTER_MASK			REG_GENMASK(30, 29)
+ #define   SPRITE_FILTER_MEDIUM			REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
+ #define   SPRITE_FILTER_ENHANCING		REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
+ #define   SPRITE_FILTER_SOFTENING		REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
+ #define   SPRITE_VERTICAL_OFFSET_HALF		REG_BIT(28) /* must be enabled below */
+ #define   SPRITE_VERTICAL_OFFSET_ENABLE		REG_BIT(27)
+ #define   SPRITE_SRC_WIDTH_MASK			REG_GENMASK(26, 16)
+ #define   SPRITE_SRC_WIDTH(w)			REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
+ #define   SPRITE_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
+ #define   SPRITE_SRC_HEIGHT(h)			REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
  #define _SPRA_GAMC		0x70400
  #define _SPRA_GAMC16		0x70440
  #define _SPRA_GAMC17		0x7044c
@@@ -7127,48 -4651,67 +4652,67 @@@
  #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
#define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
- #define   SP_ENABLE			(1 << 31)
- #define   SP_GAMMA_ENABLE		(1 << 30)
- #define   SP_PIXFORMAT_MASK		(0xf << 26)
- #define   SP_FORMAT_YUV422		(0x0 << 26)
- #define   SP_FORMAT_8BPP		(0x2 << 26)
- #define   SP_FORMAT_BGR565		(0x5 << 26)
- #define   SP_FORMAT_BGRX8888		(0x6 << 26)
- #define   SP_FORMAT_BGRA8888		(0x7 << 26)
- #define   SP_FORMAT_RGBX1010102		(0x8 << 26)
- #define   SP_FORMAT_RGBA1010102		(0x9 << 26)
- #define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
- #define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
- #define   SP_FORMAT_RGBX8888		(0xe << 26)
- #define   SP_FORMAT_RGBA8888		(0xf << 26)
- #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
- #define   SP_SOURCE_KEY			(1 << 22)
- #define   SP_YUV_FORMAT_BT709		(1 << 18)
- #define   SP_YUV_ORDER_MASK		(3 << 16)
- #define   SP_YUV_ORDER_YUYV		(0 << 16)
- #define   SP_YUV_ORDER_UYVY		(1 << 16)
- #define   SP_YUV_ORDER_YVYU		(2 << 16)
- #define   SP_YUV_ORDER_VYUY		(3 << 16)
- #define   SP_ROTATE_180			(1 << 15)
- #define   SP_TILED			(1 << 10)
- #define   SP_MIRROR			(1 << 8) /* CHV pipe B */
+ #define   SP_ENABLE			REG_BIT(31)
+ #define   SP_PIPE_GAMMA_ENABLE		REG_BIT(30)
+ #define   SP_FORMAT_MASK		REG_GENMASK(29, 26)
+ #define   SP_FORMAT_YUV422		REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+ #define   SP_FORMAT_8BPP		REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+ #define   SP_FORMAT_BGR565		REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+ #define   SP_FORMAT_BGRX8888		REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+ #define   SP_FORMAT_BGRA8888		REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+ #define   SP_FORMAT_RGBX1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 8)
+ #define   SP_FORMAT_RGBA1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 9)
+ #define   SP_FORMAT_BGRX1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
+ #define   SP_FORMAT_BGRA1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
+ #define   SP_FORMAT_RGBX8888		REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+ #define   SP_FORMAT_RGBA8888		REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+ #define   SP_ALPHA_PREMULTIPLY		REG_BIT(23) /* CHV pipe B */
+ #define   SP_SOURCE_KEY			REG_BIT(22)
+ #define   SP_YUV_FORMAT_BT709		REG_BIT(18)
+ #define   SP_YUV_ORDER_MASK		REG_GENMASK(17, 16)
+ #define   SP_YUV_ORDER_YUYV		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
+ #define   SP_YUV_ORDER_UYVY		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
+ #define   SP_YUV_ORDER_YVYU		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
+ #define   SP_YUV_ORDER_VYUY		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
+ #define   SP_ROTATE_180			REG_BIT(15)
+ #define   SP_TILED			REG_BIT(10)
+ #define   SP_MIRROR			REG_BIT(8) /* CHV pipe B */
  #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
  #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
  #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
+ #define   SP_POS_Y_MASK			REG_GENMASK(31, 16)
+ #define   SP_POS_Y(y)			REG_FIELD_PREP(SP_POS_Y_MASK, (y))
+ #define   SP_POS_X_MASK			REG_GENMASK(15, 0)
+ #define   SP_POS_X(x)			REG_FIELD_PREP(SP_POS_X_MASK, (x))
  #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
+ #define   SP_HEIGHT_MASK		REG_GENMASK(31, 16)
+ #define   SP_HEIGHT(h)			REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
+ #define   SP_WIDTH_MASK			REG_GENMASK(15, 0)
+ #define   SP_WIDTH(w)			REG_FIELD_PREP(SP_WIDTH_MASK, (w))
  #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
  #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
  #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
+ #define   SP_ADDR_MASK			REG_GENMASK(31, 12)
  #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
  #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
+ #define   SP_OFFSET_Y_MASK		REG_GENMASK(31, 16)
+ #define   SP_OFFSET_Y(y)		REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
+ #define   SP_OFFSET_X_MASK		REG_GENMASK(15, 0)
+ #define   SP_OFFSET_X(x)		REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
  #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
- #define   SP_CONST_ALPHA_ENABLE		(1 << 31)
+ #define   SP_CONST_ALPHA_ENABLE		REG_BIT(31)
+ #define   SP_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
+ #define   SP_CONST_ALPHA(alpha)		REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
  #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
- #define   SP_CONTRAST(x)		((x) << 18) /* u3.6 */
- #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
+ #define   SP_CONTRAST_MASK		REG_GENMASK(26, 18)
+ #define   SP_CONTRAST(x)		REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
+ #define   SP_BRIGHTNESS_MASK		REG_GENMASK(7, 0)
+ #define   SP_BRIGHTNESS(x)		REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
  #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
- #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
- #define   SP_SH_COS(x)			(x) /* u3.7 */
+ #define   SP_SH_SIN_MASK		REG_GENMASK(26, 16)
+ #define   SP_SH_SIN(x)			REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
+ #define   SP_SH_COS_MASK		REG_GENMASK(9, 0)
+ #define   SP_SH_COS(x)			REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
  #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
@@@ -7219,112 -4762,135 +4763,135 @@@
  #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
  #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
  #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
- #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
- #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
+ #define  SPCSC_OOFF_MASK	REG_GENMASK(26, 16)
+ #define  SPCSC_OOFF(x)		REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
+ #define  SPCSC_IOFF_MASK	REG_GENMASK(10, 0)
+ #define  SPCSC_IOFF(x)		REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
  #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
  #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
  #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
  #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
- #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
- #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
+ #define  SPCSC_C1_MASK		REG_GENMASK(30, 16)
+ #define  SPCSC_C1(x)		REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
+ #define  SPCSC_C0_MASK		REG_GENMASK(14, 0)
+ #define  SPCSC_C0(x)		REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
#define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
  #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
  #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
- #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
- #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
+ #define  SPCSC_IMAX_MASK	REG_GENMASK(26, 16)
+ #define  SPCSC_IMAX(x)		REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
+ #define  SPCSC_IMIN_MASK	REG_GENMASK(10, 0)
+ #define  SPCSC_IMIN(x)		REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
  #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
  #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
- #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
- #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
+ #define  SPCSC_OMAX_MASK	REG_GENMASK(25, 16)
+ #define  SPCSC_OMAX(x)		REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
+ #define  SPCSC_OMIN_MASK	REG_GENMASK(9, 0)
+ #define  SPCSC_OMIN(x)		REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
/* Skylake plane registers */
#define _PLANE_CTL_1_A				0x70180
  #define _PLANE_CTL_2_A				0x70280
  #define _PLANE_CTL_3_A				0x70380
- #define   PLANE_CTL_ENABLE			(1 << 31)
+ #define   PLANE_CTL_ENABLE			REG_BIT(31)
  #define   PLANE_CTL_ARB_SLOTS_MASK		REG_GENMASK(30, 28) /* icl+ */
  #define   PLANE_CTL_ARB_SLOTS(x)		REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
- #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
- #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
+ #define   PLANE_CTL_PIPE_GAMMA_ENABLE		REG_BIT(30) /* Pre-GLK */
+ #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(28)
  /*
   * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
   * expanded to include bit 23 as well. However, the shift-24 based values
   * correctly map to the same formats in ICL, as long as bit 23 is set to 0
   */
- #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
- #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
- #define   PLANE_CTL_FORMAT_NV12			(1 << 24)
- #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
- #define   PLANE_CTL_FORMAT_P010			(3 << 24)
- #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
- #define   PLANE_CTL_FORMAT_P012			(5 << 24)
- #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
- #define   PLANE_CTL_FORMAT_P016			(7 << 24)
- #define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
- #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
- #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
- #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
- #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
- #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
- #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
- #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
- #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
- #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
- #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
- #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
- #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
- #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
- #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
- #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
- #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
- #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
- #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
- #define   PLANE_CTL_YUV422_ORDER_YUYV		(0 << 16)
- #define   PLANE_CTL_YUV422_ORDER_UYVY		(1 << 16)
- #define   PLANE_CTL_YUV422_ORDER_YVYU		(2 << 16)
- #define   PLANE_CTL_YUV422_ORDER_VYUY		(3 << 16)
- #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
- #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
- #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
- #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
- #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
- #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
- #define   PLANE_CTL_TILED_X			(1 << 10)
- #define   PLANE_CTL_TILED_Y			(4 << 10)
- #define   PLANE_CTL_TILED_YF			(5 << 10)
- #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
- #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
- #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
- #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
- #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
- #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
- #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(3 << 4)
- #define   PLANE_CTL_ROTATE_MASK			0x3
- #define   PLANE_CTL_ROTATE_0			0x0
- #define   PLANE_CTL_ROTATE_90			0x1
- #define   PLANE_CTL_ROTATE_180			0x2
- #define   PLANE_CTL_ROTATE_270			0x3
+ #define   PLANE_CTL_FORMAT_MASK_SKL		REG_GENMASK(27, 24) /* pre-icl */
+ #define   PLANE_CTL_FORMAT_MASK_ICL		REG_GENMASK(27, 23) /* icl+ */
+ #define   PLANE_CTL_FORMAT_YUV422		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+ #define   PLANE_CTL_FORMAT_NV12			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+ #define   PLANE_CTL_FORMAT_XRGB_2101010		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+ #define   PLANE_CTL_FORMAT_P010			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+ #define   PLANE_CTL_FORMAT_XRGB_8888		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+ #define   PLANE_CTL_FORMAT_P012			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+ #define   PLANE_CTL_FORMAT_XRGB_16161616F	REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+ #define   PLANE_CTL_FORMAT_P016			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+ #define   PLANE_CTL_FORMAT_XYUV			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+ #define   PLANE_CTL_FORMAT_INDEXED		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+ #define   PLANE_CTL_FORMAT_RGB_565		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+ #define   PLANE_CTL_FORMAT_Y210			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+ #define   PLANE_CTL_FORMAT_Y212			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
+ #define   PLANE_CTL_FORMAT_Y216			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
+ #define   PLANE_CTL_FORMAT_Y410			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
+ #define   PLANE_CTL_FORMAT_Y412			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
+ #define   PLANE_CTL_FORMAT_Y416			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
+ #define   PLANE_CTL_PIPE_CSC_ENABLE		REG_BIT(23) /* Pre-GLK */
+ #define   PLANE_CTL_KEY_ENABLE_MASK		REG_GENMASK(22, 21)
+ #define   PLANE_CTL_KEY_ENABLE_SOURCE		REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
+ #define   PLANE_CTL_KEY_ENABLE_DESTINATION	REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
+ #define   PLANE_CTL_ORDER_RGBX			REG_BIT(20)
+ #define   PLANE_CTL_YUV420_Y_PLANE		REG_BIT(19)
+ #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	REG_BIT(18)
+ #define   PLANE_CTL_YUV422_ORDER_MASK		REG_GENMASK(17, 16)
+ #define   PLANE_CTL_YUV422_ORDER_YUYV		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
+ #define   PLANE_CTL_YUV422_ORDER_UYVY		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
+ #define   PLANE_CTL_YUV422_ORDER_YVYU		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
+ #define   PLANE_CTL_YUV422_ORDER_VYUY		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
+ #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	REG_BIT(15)
+ #define   PLANE_CTL_TRICKLE_FEED_DISABLE	REG_BIT(14)
+ #define   PLANE_CTL_CLEAR_COLOR_DISABLE		REG_BIT(13) /* TGL+ */
+ #define   PLANE_CTL_PLANE_GAMMA_DISABLE		REG_BIT(13) /* Pre-GLK */
+ #define   PLANE_CTL_TILED_MASK			REG_GENMASK(12, 10)
+ #define   PLANE_CTL_TILED_LINEAR		REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
+ #define   PLANE_CTL_TILED_X			REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
+ #define   PLANE_CTL_TILED_Y			REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
+ #define   PLANE_CTL_TILED_YF			REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+ #define   PLANE_CTL_ASYNC_FLIP			REG_BIT(9)
+ #define   PLANE_CTL_FLIP_HORIZONTAL		REG_BIT(8)
+ #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	REG_BIT(4) /* TGL+ */
+ #define   PLANE_CTL_ALPHA_MASK			REG_GENMASK(5, 4) /* Pre-GLK */
+ #define   PLANE_CTL_ALPHA_DISABLE		REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
+ #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
+ #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
+ #define   PLANE_CTL_ROTATE_MASK			REG_GENMASK(1, 0)
+ #define   PLANE_CTL_ROTATE_0			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
+ #define   PLANE_CTL_ROTATE_90			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
+ #define   PLANE_CTL_ROTATE_180			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
+ #define   PLANE_CTL_ROTATE_270			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
  #define _PLANE_STRIDE_1_A			0x70188
  #define _PLANE_STRIDE_2_A			0x70288
  #define _PLANE_STRIDE_3_A			0x70388
+ #define   PLANE_STRIDE__MASK			REG_GENMASK(11, 0)
+ #define   PLANE_STRIDE_(stride)			REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
  #define _PLANE_POS_1_A				0x7018c
  #define _PLANE_POS_2_A				0x7028c
  #define _PLANE_POS_3_A				0x7038c
+ #define   PLANE_POS_Y_MASK			REG_GENMASK(31, 16)
+ #define   PLANE_POS_Y(y)			REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
+ #define   PLANE_POS_X_MASK			REG_GENMASK(15, 0)
+ #define   PLANE_POS_X(x)			REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
  #define _PLANE_SIZE_1_A				0x70190
  #define _PLANE_SIZE_2_A				0x70290
  #define _PLANE_SIZE_3_A				0x70390
+ #define   PLANE_HEIGHT_MASK			REG_GENMASK(31, 16)
+ #define   PLANE_HEIGHT(h)			REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
+ #define   PLANE_WIDTH_MASK			REG_GENMASK(15, 0)
+ #define   PLANE_WIDTH(w)			REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
  #define _PLANE_SURF_1_A				0x7019c
  #define _PLANE_SURF_2_A				0x7029c
  #define _PLANE_SURF_3_A				0x7039c
+ #define   PLANE_SURF_ADDR_MASK			REG_GENMASK(31, 12)
+ #define   PLANE_SURF_DECRYPT			REG_BIT(2)
  #define _PLANE_OFFSET_1_A			0x701a4
  #define _PLANE_OFFSET_2_A			0x702a4
  #define _PLANE_OFFSET_3_A			0x703a4
+ #define   PLANE_OFFSET_Y_MASK			REG_GENMASK(31, 16)
+ #define   PLANE_OFFSET_Y(y)			REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
+ #define   PLANE_OFFSET_X_MASK			REG_GENMASK(15, 0)
+ #define   PLANE_OFFSET_X(x)			REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
  #define _PLANE_KEYVAL_1_A			0x70194
  #define _PLANE_KEYVAL_2_A			0x70294
  #define _PLANE_KEYMSK_1_A			0x70198
@@@ -7336,42 -4902,49 +4903,49 @@@
  #define _PLANE_CC_VAL_1_A			0x701b4
  #define _PLANE_CC_VAL_2_A			0x702b4
  #define _PLANE_AUX_DIST_1_A			0x701c0
+ #define   PLANE_AUX_DISTANCE_MASK		REG_GENMASK(31, 12)
+ #define   PLANE_AUX_STRIDE_MASK			REG_GENMASK(11, 0)
+ #define   PLANE_AUX_STRIDE(stride)		REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
  #define _PLANE_AUX_DIST_2_A			0x702c0
  #define _PLANE_AUX_OFFSET_1_A			0x701c4
  #define _PLANE_AUX_OFFSET_2_A			0x702c4
  #define _PLANE_CUS_CTL_1_A			0x701c8
  #define _PLANE_CUS_CTL_2_A			0x702c8
- #define  PLANE_CUS_ENABLE			(1 << 31)
- #define  PLANE_CUS_Y_PLANE_4_RKL		(0 << 30)
- #define  PLANE_CUS_Y_PLANE_5_RKL		(1 << 30)
- #define  PLANE_CUS_Y_PLANE_6_ICL		(0 << 30)
- #define  PLANE_CUS_Y_PLANE_7_ICL		(1 << 30)
- #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
- #define  PLANE_CUS_HPHASE_0			(0 << 16)
- #define  PLANE_CUS_HPHASE_0_25			(1 << 16)
- #define  PLANE_CUS_HPHASE_0_5			(2 << 16)
- #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE		(1 << 15)
- #define  PLANE_CUS_VPHASE_0			(0 << 12)
- #define  PLANE_CUS_VPHASE_0_25			(1 << 12)
- #define  PLANE_CUS_VPHASE_0_5			(2 << 12)
+ #define   PLANE_CUS_ENABLE			REG_BIT(31)
+ #define   PLANE_CUS_Y_PLANE_MASK			REG_BIT(30)
+ #define   PLANE_CUS_Y_PLANE_4_RKL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+ #define   PLANE_CUS_Y_PLANE_5_RKL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+ #define   PLANE_CUS_Y_PLANE_6_ICL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+ #define   PLANE_CUS_Y_PLANE_7_ICL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+ #define   PLANE_CUS_HPHASE_SIGN_NEGATIVE		REG_BIT(19)
+ #define   PLANE_CUS_HPHASE_MASK			REG_GENMASK(17, 16)
+ #define   PLANE_CUS_HPHASE_0			REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
+ #define   PLANE_CUS_HPHASE_0_25			REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
+ #define   PLANE_CUS_HPHASE_0_5			REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
+ #define   PLANE_CUS_VPHASE_SIGN_NEGATIVE		REG_BIT(15)
+ #define   PLANE_CUS_VPHASE_MASK			REG_GENMASK(13, 12)
+ #define   PLANE_CUS_VPHASE_0			REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
+ #define   PLANE_CUS_VPHASE_0_25			REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
+ #define   PLANE_CUS_VPHASE_0_5			REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
  #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
  #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
  #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
- #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
- #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
+ #define   PLANE_COLOR_PIPE_GAMMA_ENABLE			REG_BIT(30) /* Pre-ICL */
+ #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(28)
+ #define   PLANE_COLOR_PIPE_CSC_ENABLE			REG_BIT(23) /* Pre-ICL */
  #define   PLANE_COLOR_PLANE_CSC_ENABLE			REG_BIT(21) /* ICL+ */
- #define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
- #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
- #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
- #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601		(1 << 17)
- #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		(2 << 17)
- #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
- #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
- #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
- #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
- #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
- #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY	(2 << 4)
- #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY	(3 << 4)
+ #define   PLANE_COLOR_INPUT_CSC_ENABLE			REG_BIT(20) /* ICL+ */
+ #define   PLANE_COLOR_CSC_MODE_MASK			REG_GENMASK(19, 17)
+ #define   PLANE_COLOR_CSC_MODE_BYPASS			REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
+ #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601		REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
+ #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
+ #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
+ #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
+ #define   PLANE_COLOR_PLANE_GAMMA_DISABLE		REG_BIT(13)
+ #define   PLANE_COLOR_ALPHA_MASK			REG_GENMASK(5, 4)
+ #define   PLANE_COLOR_ALPHA_DISABLE			REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
+ #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY		REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
+ #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY		REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
  #define _PLANE_BUF_CFG_1_A			0x7027c
  #define _PLANE_BUF_CFG_2_A			0x7037c
  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
@@@ -7454,8 -5027,6 +5028,6 @@@
    _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
  #define PLANE_STRIDE(pipe, plane)	\
    _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
- #define PLANE_STRIDE_MASK		REG_GENMASK(10, 0)
- #define PLANE_STRIDE_MASK_XELPD		REG_GENMASK(11, 0)
#define _PLANE_POS_1_B				0x7118c
  #define _PLANE_POS_2_B				0x7128c
@@@ -7483,7 -5054,6 +5055,6 @@@
  #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
  #define PLANE_SURF(pipe, plane)	\
    _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
- #define   PLANE_SURF_DECRYPT			REG_BIT(2)
#define _PLANE_OFFSET_1_B			0x711a4
  #define _PLANE_OFFSET_2_B			0x712a4
@@@ -7515,8 -5085,11 +5086,11 @@@
#define _PLANE_BUF_CFG_1_B			0x7127c
  #define _PLANE_BUF_CFG_2_B			0x7137c
- #define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
- #define  DDB_ENTRY_END_SHIFT			16
+ /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+ #define   PLANE_BUF_END_MASK		REG_GENMASK(27, 16)
+ #define   PLANE_BUF_END(end)		REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+ #define   PLANE_BUF_START_MASK		REG_GENMASK(11, 0)
+ #define   PLANE_BUF_START(start)	REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
  #define _PLANE_BUF_CFG_1(pipe)	\
    _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
  #define _PLANE_BUF_CFG_2(pipe)	\
@@@ -7671,24 -5244,13 +5245,13 @@@
#define _PIPEA_DATA_M1		0x60030
- #define  PIPE_DATA_M1_OFFSET    0
  #define _PIPEA_DATA_N1		0x60034
- #define  PIPE_DATA_N1_OFFSET    0
- 
  #define _PIPEA_DATA_M2		0x60038
- #define  PIPE_DATA_M2_OFFSET    0
  #define _PIPEA_DATA_N2		0x6003c
- #define  PIPE_DATA_N2_OFFSET    0
- 
  #define _PIPEA_LINK_M1		0x60040
- #define  PIPE_LINK_M1_OFFSET    0
  #define _PIPEA_LINK_N1		0x60044
- #define  PIPE_LINK_N1_OFFSET    0
- 
  #define _PIPEA_LINK_M2		0x60048
- #define  PIPE_LINK_M2_OFFSET    0
  #define _PIPEA_LINK_N2		0x6004c
- #define  PIPE_LINK_N2_OFFSET    0
/* PIPEB timing regs are same start from 0x61000 */
@@@ -7945,7 -5507,8 +5508,8 @@@
  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
  #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
- #define DMC_DEBUG3		_MMIO(0x101090)
+ #define TGL_DMC_DEBUG3		_MMIO(0x101090)
+ #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
/* Display Internal Timeout Register */
  #define RM_TIMEOUT		_MMIO(0x42060)
@@@ -8200,63 -5763,6 +5764,6 @@@
  #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
  #define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
- #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
- #define  GEN11_CSME			(31)
- #define  GEN11_GUNIT			(28)
- #define  GEN11_GUC			(25)
- #define  GEN11_WDPERF			(20)
- #define  GEN11_KCR			(19)
- #define  GEN11_GTPM			(16)
- #define  GEN11_BCS			(15)
- #define  GEN11_RCS0			(0)
- 
- #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
- #define  GEN11_VECS(x)			(31 - (x))
- #define  GEN11_VCS(x)			(x)
- 
- #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
- 
- #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
- #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
- #define  GEN11_INTR_DATA_VALID		(1 << 31)
- #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
- #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
- #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
- /* irq instances for OTHER_CLASS */
- #define OTHER_GUC_INSTANCE	0
- #define OTHER_GTPM_INSTANCE	1
- #define OTHER_KCR_INSTANCE	4
- 
- #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
- 
- #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
- #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
- 
- #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
- 
- #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
- #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
- #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
- #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
- #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
- #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
- 
- #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
- #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
- #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
- #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
- #define GEN12_VCS4_VCS5_INTR_MASK	_MMIO(0x1900b0)
- #define GEN12_VCS6_VCS7_INTR_MASK	_MMIO(0x1900b4)
- #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
- #define GEN12_VECS2_VECS3_INTR_MASK	_MMIO(0x1900d4)
- #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
- #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
- #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
- #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
- 
- #define   ENGINE1_MASK			REG_GENMASK(31, 16)
- #define   ENGINE0_MASK			REG_GENMASK(15, 0)
- 
  #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
  #define  ILK_ELPIN_409_SELECT	(1 << 25)
@@@ -8410,11 -5916,14 +5917,14 @@@
  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
- #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
- #define   SKL_SELECT_ALTERNATE_DC_EXIT	REG_BIT(30)
- #define   ICL_DELAY_PMRSP		REG_BIT(22)
- #define   DISABLE_FLR_SRC		REG_BIT(15)
- #define   MASK_WAKEMEM			REG_BIT(13)
+ #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
+ #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
+ #define   LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
+ #define   LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
+ #define   LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
+ #define   ICL_DELAY_PMRSP			REG_BIT(22)
+ #define   DISABLE_FLR_SRC			REG_BIT(15)
+ #define   MASK_WAKEMEM				REG_BIT(13)
#define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
  #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR	REG_BIT(27)
@@@ -8443,142 -5952,6 +5953,6 @@@
  #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
  #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
- #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
- #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1 << 14)
- 
- #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
- #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
- #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
- 
- #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
- #define   FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(1)
- #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
- #define   GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
- 
- #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON		_MMIO(0x20EC)
- #define   GEN12_REPLAY_MODE_GRANULARITY			REG_BIT(0)
- 
- #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
- #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
- #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)	(((hi) << 2) | ((lo) << 1))
- #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
- #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
- #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
- #define GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
- 
- /* GEN7 chicken */
- #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
-   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	(1 << 10)
-   #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
- 
- #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
-   #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
-   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
-   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
-   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
- 
- #define GEN8_L3CNTLREG	_MMIO(0x7034)
-   #define GEN8_ERRDETBCTRL (1 << 9)
- 
- #define GEN11_COMMON_SLICE_CHICKEN3			_MMIO(0x7304)
- #define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
- #define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
- #define   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC		REG_BIT(11)
- #define   GEN12_DISABLE_CPS_AWARE_COLOR_PIPE		REG_BIT(9)
- 
- #define HIZ_CHICKEN					_MMIO(0x7018)
- # define CHV_HZ_8X8_MODE_IN_1X				REG_BIT(15)
- # define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE   REG_BIT(14)
- # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
- 
- #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
- #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
- 
- #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
- #define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
- 
- #define GEN7_SARCHKMD				_MMIO(0xB000)
- #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
- #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
- 
- #define GEN7_L3SQCREG1				_MMIO(0xB010)
- #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
- 
- #define GEN8_L3SQCREG1				_MMIO(0xB100)
- /*
-  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
-  * Using the formula in BSpec leads to a hang, while the formula here works
-  * fine and matches the formulas for all other platforms. A BSpec change
-  * request has been filed to clarify this.
-  */
- #define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)
- #define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)
- #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
- 
- #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
- #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
- #define  GEN7_L3AGDIS				(1 << 19)
- #define GEN7_L3CNTLREG2				_MMIO(0xB020)
- #define GEN7_L3CNTLREG3				_MMIO(0xB024)
- 
- #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
- #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
- #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
- #define   GEN11_I2M_WRITE_DISABLE		(1 << 28)
- 
- #define GEN7_L3SQCREG4				_MMIO(0xb034)
- #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
- 
- #define GEN11_SCRATCH2					_MMIO(0xb140)
- #define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE	(1 << 19)
- 
- #define GEN8_L3SQCREG4				_MMIO(0xb118)
- #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
- #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
- #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
- #define  GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
- 
- #define GEN11_L3SQCREG5				_MMIO(0xb158)
- #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
- 
- #define XEHP_L3SCQREG7				_MMIO(0xb188)
- #define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
- 
- /* GEN8 chicken */
- #define HDC_CHICKEN0				_MMIO(0x7300)
- #define ICL_HDC_MODE				_MMIO(0xE5F4)
- #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
- #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
- #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
- #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
- #define  HDC_FORCE_NON_COHERENT			(1 << 4)
- #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
- 
- #define GEN12_HDC_CHICKEN0					_MMIO(0xE5F0)
- #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
- 
- #define SARB_CHICKEN1				_MMIO(0xe90c)
- #define   COMP_CKN_IN				REG_GENMASK(30, 29)
- 
- #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
- 
- /* GEN9 chicken */
- #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
- #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
- 
- #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
- #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
- 
- /* WaCatErrorRejectionIssue */
- #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
- #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1 << 11)
- 
- #define HSW_SCRATCH1				_MMIO(0xb038)
- #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1 << 27)
- 
- #define BDW_SCRATCH1					_MMIO(0xb11c)
- #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
- 
  /*GEN11 chicken */
  #define _PIPEA_CHICKEN				0x70038
  #define _PIPEB_CHICKEN				0x71038
@@@ -8591,16 -5964,6 +5965,6 @@@
  #define   DG2_RENDER_CCSTAG_4_3_EN		REG_BIT(12)
  #define   PER_PIXEL_ALPHA_BYPASS_EN		REG_BIT(7)
- #define VFLSKPD				_MMIO(0x62a8)
- #define   DIS_OVER_FETCH_CACHE		REG_BIT(1)
- #define   DIS_MULT_MISS_RD_SQUASH	REG_BIT(0)
- 
- #define FF_MODE2			_MMIO(0x6604)
- #define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)
- #define   FF_MODE2_GS_TIMER_224		REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
- #define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
- #define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
- 
  /* PCH */
#define PCH_DISPLAY_BASE	0xc0000u
@@@ -8697,6 -6060,7 +6061,7 @@@
  /* south display engine interrupt: ICP/TGP */
  #define SDE_GMBUS_ICP			(1 << 23)
  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+ #define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
    				 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
@@@ -9015,22 -6379,19 +6380,19 @@@
  #define _PCH_TRANSBCONF              0xf1008
  #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
  #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
- #define  TRANS_DISABLE          (0 << 31)
- #define  TRANS_ENABLE           (1 << 31)
- #define  TRANS_STATE_MASK       (1 << 30)
- #define  TRANS_STATE_DISABLE    (0 << 30)
- #define  TRANS_STATE_ENABLE     (1 << 30)
- #define  TRANS_FRAME_START_DELAY_MASK	(3 << 27) /* ibx */
- #define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
- #define  TRANS_INTERLACE_MASK   (7 << 21)
- #define  TRANS_PROGRESSIVE      (0 << 21)
- #define  TRANS_INTERLACED       (3 << 21)
- #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
- #define  TRANS_8BPC             (0 << 5)
- #define  TRANS_10BPC            (1 << 5)
- #define  TRANS_6BPC             (2 << 5)
- #define  TRANS_12BPC            (3 << 5)
- 
+ #define  TRANS_ENABLE			REG_BIT(31)
+ #define  TRANS_STATE_ENABLE		REG_BIT(30)
+ #define  TRANS_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27) /* ibx */
+ #define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+ #define  TRANS_INTERLACE_MASK		REG_GENMASK(23, 21)
+ #define  TRANS_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+ #define  TRANS_INTERLACE_LEGACY_VSYNC_IBX	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+ #define  TRANS_INTERLACE_INTERLACED	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+ #define  TRANS_BPC_MASK			REG_GENMASK(7, 5) /* ibx */
+ #define  TRANS_BPC_8			REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+ #define  TRANS_BPC_10			REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+ #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+ #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
  #define _TRANSA_CHICKEN1	 0xf0060
  #define _TRANSB_CHICKEN1	 0xf1060
  #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
@@@ -9240,22 -6601,19 +6602,19 @@@
  #define _TRANS_DP_CTL_B		0xe1300
  #define _TRANS_DP_CTL_C		0xe2300
  #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
- #define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
- #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
- #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
- #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
- #define  TRANS_DP_AUDIO_ONLY	(1 << 26)
- #define  TRANS_DP_ENH_FRAMING	(1 << 18)
- #define  TRANS_DP_8BPC		(0 << 9)
- #define  TRANS_DP_10BPC		(1 << 9)
- #define  TRANS_DP_6BPC		(2 << 9)
- #define  TRANS_DP_12BPC		(3 << 9)
- #define  TRANS_DP_BPC_MASK	(3 << 9)
- #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
- #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
- #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
- #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
- #define  TRANS_DP_SYNC_MASK	(3 << 3)
+ #define  TRANS_DP_OUTPUT_ENABLE		REG_BIT(31)
+ #define  TRANS_DP_PORT_SEL_MASK		REG_GENMASK(30, 29)
+ #define  TRANS_DP_PORT_SEL_NONE		REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
+ #define  TRANS_DP_PORT_SEL(port)	REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
+ #define  TRANS_DP_AUDIO_ONLY		REG_BIT(26)
+ #define  TRANS_DP_ENH_FRAMING		REG_BIT(18)
+ #define  TRANS_DP_BPC_MASK		REG_GENMASK(10, 9)
+ #define  TRANS_DP_BPC_8			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
+ #define  TRANS_DP_BPC_10		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
+ #define  TRANS_DP_BPC_6			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
+ #define  TRANS_DP_BPC_12		REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
+ #define  TRANS_DP_VSYNC_ACTIVE_HIGH	REG_BIT(4)
+ #define  TRANS_DP_HSYNC_ACTIVE_HIGH	REG_BIT(3)
#define _TRANS_DP2_CTL_A			0x600a0
  #define _TRANS_DP2_CTL_B			0x610a0
@@@ -9314,261 -6672,16 +6673,16 @@@
#define  VLV_PMWGICZ				_MMIO(0x1300a4)
- #define  RC6_LOCATION				_MMIO(0xD40)
- #define	   RC6_CTX_IN_DRAM			(1 << 0)
- #define  RC6_CTX_BASE				_MMIO(0xD48)
- #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
- #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
- #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
- #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
- #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
- #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
- #define    IDLE_TIME_MASK			0xFFFFF
- #define  FORCEWAKE				_MMIO(0xA18C)
- #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
- #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
- #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
- #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
- #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
- #define  FORCEWAKE_ACK				_MMIO(0x130090)
- #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
- #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
- #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
- #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
- 
- #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
- #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
- #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
- #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
- #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
- #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
- #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
- #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
- #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
- #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
- #define  FORCEWAKE_GT_GEN9			_MMIO(0xa188)
- #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
- #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
- #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
- #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
- #define  FORCEWAKE_ACK_GT_GEN9			_MMIO(0x130044)
- #define   FORCEWAKE_KERNEL			BIT(0)
- #define   FORCEWAKE_USER			BIT(1)
- #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
- #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
- #define  ECOBUS					_MMIO(0xa180)
- #define    FORCEWAKE_MT_ENABLE			(1 << 5)
- #define  VLV_SPAREG2H				_MMIO(0xA194)
- #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
- #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
- #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
- 
- #define  GTFIFODBG				_MMIO(0x120000)
- #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
- #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
- #define    GT_FIFO_SBDROPERR			(1 << 6)
- #define    GT_FIFO_BLOBDROPERR			(1 << 5)
- #define    GT_FIFO_SB_READ_ABORTERR		(1 << 4)
- #define    GT_FIFO_DROPERR			(1 << 3)
- #define    GT_FIFO_OVFERR			(1 << 2)
- #define    GT_FIFO_IAWRERR			(1 << 1)
- #define    GT_FIFO_IARDERR			(1 << 0)
- 
- #define  GTFIFOCTL				_MMIO(0x120008)
- #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
- #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
- #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
- #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
- 
- #define  HSW_IDICR				_MMIO(0x9008)
- #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
  #define  HSW_EDRAM_CAP				_MMIO(0x120010)
  #define    EDRAM_ENABLED			0x1
  #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
  #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
  #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
- #define GEN6_UCGCTL1				_MMIO(0x9400)
- # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
- # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
- # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
- # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
- 
- #define GEN6_UCGCTL2				_MMIO(0x9404)
- # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
- # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
- # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
- # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
- # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
- # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
- 
- #define GEN6_UCGCTL3				_MMIO(0x9408)
- # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE		(1 << 20)
- 
- #define GEN7_UCGCTL4				_MMIO(0x940c)
- #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1 << 25)
- #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1 << 14)
- 
- #define GEN6_RCGCTL1				_MMIO(0x9410)
- #define GEN6_RCGCTL2				_MMIO(0x9414)
- #define GEN6_RSTCTL				_MMIO(0x9420)
- 
- #define GEN8_UCGCTL6				_MMIO(0x9430)
- #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1 << 24)
- #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1 << 14)
- #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
- 
- #define UNSLCGCTL9430				_MMIO(0x9430)
- #define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
- 
- #define GEN6_GFXPAUSE				_MMIO(0xA000)
- #define GEN6_RPNSWREQ				_MMIO(0xA008)
- #define   GEN6_TURBO_DISABLE			(1 << 31)
- #define   GEN6_FREQUENCY(x)			((x) << 25)
- #define   HSW_FREQUENCY(x)			((x) << 24)
- #define   GEN9_FREQUENCY(x)			((x) << 23)
- #define   GEN6_OFFSET(x)			((x) << 19)
- #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
- #define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT	23
- #define   GEN9_IGNORE_SLICE_RATIO		(0 << 0)
- 
- #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
- #define GEN6_RC_CONTROL				_MMIO(0xA090)
- #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
- #define   GEN6_RC_CTL_RC6p_ENABLE		(1 << 17)
- #define   GEN6_RC_CTL_RC6_ENABLE		(1 << 18)
- #define   GEN6_RC_CTL_RC1e_ENABLE		(1 << 20)
- #define   GEN6_RC_CTL_RC7_ENABLE		(1 << 22)
- #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1 << 24)
- #define   GEN7_RC_CTL_TO_MODE			(1 << 28)
- #define   GEN6_RC_CTL_EI_MODE(x)		((x) << 27)
- #define   GEN6_RC_CTL_HW_ENABLE			(1 << 31)
- #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
- #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
- #define GEN6_RPSTAT1				_MMIO(0xA01C)
- #define   GEN6_CAGF_SHIFT			8
- #define   HSW_CAGF_SHIFT			7
- #define   GEN9_CAGF_SHIFT			23
- #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
- #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
- #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
- #define GEN6_RP_CONTROL				_MMIO(0xA024)
- #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
- #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
- #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3 << 9)
- #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2 << 9)
- #define   GEN6_RP_MEDIA_HW_MODE			(1 << 9)
- #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
- #define   GEN6_RP_MEDIA_IS_GFX			(1 << 8)
- #define   GEN6_RP_ENABLE			(1 << 7)
- #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
- #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
- #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
- #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
- #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
- #define   GEN6_RPSWCTL_SHIFT			9
- #define   GEN9_RPSWCTL_ENABLE			(0x2 << GEN6_RPSWCTL_SHIFT)
- #define   GEN9_RPSWCTL_DISABLE			(0x0 << GEN6_RPSWCTL_SHIFT)
- #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
- #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
- #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
- #define   GEN6_RP_EI_MASK			0xffffff
- #define   GEN6_CURICONT_MASK			GEN6_RP_EI_MASK
- #define GEN6_RP_CUR_UP				_MMIO(0xA054)
- #define   GEN6_CURBSYTAVG_MASK			GEN6_RP_EI_MASK
- #define GEN6_RP_PREV_UP				_MMIO(0xA058)
- #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
- #define   GEN6_CURIAVG_MASK			GEN6_RP_EI_MASK
- #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
- #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
- #define GEN6_RP_UP_EI				_MMIO(0xA068)
- #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
- #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
- #define GEN6_RPDEUHWTC				_MMIO(0xA080)
- #define GEN6_RPDEUC				_MMIO(0xA084)
- #define GEN6_RPDEUCSW				_MMIO(0xA088)
- #define GEN6_RC_STATE				_MMIO(0xA094)
- #define   RC_SW_TARGET_STATE_SHIFT		16
- #define   RC_SW_TARGET_STATE_MASK		(7 << RC_SW_TARGET_STATE_SHIFT)
- #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
- #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
- #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
- #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
- #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
- #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
- #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
- #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
- #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
- #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
- #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
- #define VLV_RCEDATA				_MMIO(0xA0BC)
- #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
- #define GEN6_PMINTRMSK				_MMIO(0xA168)
- #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC	(1 << 31)
- #define   ARAT_EXPIRED_INTRMSK			(1 << 9)
- #define GEN8_MISC_CTRL0				_MMIO(0xA180)
- #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
- #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
- #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
- #define GEN9_PG_ENABLE				_MMIO(0xA210)
- #define   GEN9_RENDER_PG_ENABLE			REG_BIT(0)
- #define   GEN9_MEDIA_PG_ENABLE			REG_BIT(1)
- #define   GEN11_MEDIA_SAMPLER_PG_ENABLE		REG_BIT(2)
- #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
- #define   VDN_MFX_POWERGATE_ENABLE(n)		REG_BIT(4 + 2 * (n))
- #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
- #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
- #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
- 
  #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
  #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
  #define  PIXEL_OVERLAP_CNT_SHIFT		30
- #define GEN6_PMISR				_MMIO(0x44020)
- #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
- #define GEN6_PMIIR				_MMIO(0x44028)
- #define GEN6_PMIER				_MMIO(0x4402C)
- #define  GEN6_PM_MBOX_EVENT			(1 << 25)
- #define  GEN6_PM_THERMAL_EVENT			(1 << 24)
- 
- /*
-  * For Gen11 these are in the upper word of the GPM_WGBOXPERF
-  * registers. Shifting is handled on accessing the imr and ier.
-  */
- #define  GEN6_PM_RP_DOWN_TIMEOUT		(1 << 6)
- #define  GEN6_PM_RP_UP_THRESHOLD		(1 << 5)
- #define  GEN6_PM_RP_DOWN_THRESHOLD		(1 << 4)
- #define  GEN6_PM_RP_UP_EI_EXPIRED		(1 << 2)
- #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1 << 1)
- #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_EI_EXPIRED   | \
- 						 GEN6_PM_RP_UP_THRESHOLD    | \
- 						 GEN6_PM_RP_DOWN_EI_EXPIRED | \
- 						 GEN6_PM_RP_DOWN_THRESHOLD  | \
- 						 GEN6_PM_RP_DOWN_TIMEOUT)
- 
- #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
- #define GEN7_GT_SCRATCH_REG_NUM			8
- 
- #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
- #define VLV_GFX_CLK_STATUS_BIT			(1 << 3)
- #define VLV_GFX_CLK_FORCE_ON_BIT		(1 << 2)
- 
- #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
- #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
- #define   VLV_COUNT_RANGE_HIGH			(1 << 15)
- #define   VLV_MEDIA_RC0_COUNT_EN		(1 << 5)
- #define   VLV_RENDER_RC0_COUNT_EN		(1 << 4)
- #define   VLV_MEDIA_RC6_COUNT_EN		(1 << 1)
- #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
- #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
- #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
- #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
- 
- #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
- #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
- #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
- #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
- 
  #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
  #define   GEN6_PCODE_READY			(1 << 31)
  #define   GEN6_PCODE_ERROR_MASK			0xFF
@@@ -9635,82 -6748,6 +6749,6 @@@
  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
  #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
- #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
- #define   GEN6_CORE_CPD_STATE_MASK	(7 << 4)
- #define   GEN6_RCn_MASK			7
- #define   GEN6_RC0			0
- #define   GEN6_RC3			2
- #define   GEN6_RC6			3
- #define   GEN6_RC7			4
- 
- #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
- #define   GEN8_LSLICESTAT_MASK		0x7
- 
- #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
- #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
- #define   CHV_SS_PG_ENABLE		(1 << 1)
- #define   CHV_EU08_PG_ENABLE		(1 << 9)
- #define   CHV_EU19_PG_ENABLE		(1 << 17)
- #define   CHV_EU210_PG_ENABLE		(1 << 25)
- 
- #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
- #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
- #define   CHV_EU311_PG_ENABLE		(1 << 1)
- 
- #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
- #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
- 					      ((slice) % 3) * 0x4)
- #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
- #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
- #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
- 
- #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
- #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
- 					      ((slice) % 3) * 0x8)
- #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
- #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
- 					      ((slice) % 3) * 0x8)
- #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
- #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
- #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
- #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
- #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
- #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
- #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
- #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
- 
- #define GEN7_MISCCPCTL				_MMIO(0x9424)
- #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
- #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
- #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
- #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
- 
- #define GEN8_GARBCNTL				_MMIO(0xB004)
- #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
- #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
- #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
- #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
- 
- #define GEN11_GLBLINVL				_MMIO(0xB404)
- #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
- #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
- 
- #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
- #define   DFR_DISABLE			(1 << 9)
- 
- #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
- #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
- #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
- #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
- 
- #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
- #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC	(1 << 9)
- #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
- 
- #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
- #define   ENABLE_SMALLPL			REG_BIT(15)
- #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
- 
  /* IVYBRIDGE DPF */
  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
@@@ -9725,73 -6762,6 +6763,6 @@@
    	(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
  #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
- #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
- #define GEN7_L3LOG_SIZE			0x80
- 
- #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
- #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
- #define   GEN7_MAX_PS_THREAD_DEP		(8 << 12)
- #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1 << 10)
- #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1 << 4)
- #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1 << 3)
- 
- #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
- #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
- #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
- 
- #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
- #define   FLOW_CONTROL_ENABLE			REG_BIT(15)
- #define   UGM_BACKUP_MODE			REG_BIT(13)
- #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
- #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	REG_BIT(8)
- #define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
- #define   THROTTLE_12_5				REG_GENMASK(4, 2)
- #define   DISABLE_EARLY_EOT			REG_BIT(1)
- 
- #define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
- #define   GEN12_DISABLE_READ_SUPPRESSION	REG_BIT(15)
- #define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)
- #define   GEN12_ENABLE_LARGE_GRF_MODE		REG_BIT(12)
- #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)
- 
- #define LSC_CHICKEN_BIT_0			_MMIO(0xe7c8)
- #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
- #define LSC_CHICKEN_BIT_0_UDW			_MMIO(0xe7c8 + 4)
- #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
- #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
- #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
- #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
- #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
- 
- #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
- #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
- #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
- #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
- 
- #define GEN9_ROW_CHICKEN4				_MMIO(0xe48c)
- #define   GEN12_DISABLE_GRF_CLEAR			REG_BIT(13)
- #define   GEN12_DISABLE_TDL_PUSH			REG_BIT(9)
- #define   GEN11_DIS_PICK_2ND_EU				REG_BIT(7)
- #define   GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
- 
- #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
- #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
- 
- #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
- #define   GEN8_ST_PO_DISABLE		(1 << 13)
- 
- #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
- #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
- #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
- #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
- #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
- 
- #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
- #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
- #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	REG_BIT(8)
- #define   GEN9_ENABLE_YV12_BUGFIX			REG_BIT(4)
- #define   GEN9_ENABLE_GPGPU_PREEMPTION			REG_BIT(2)
- 
  /* Audio */
  #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
  #define   INTEL_AUDIO_DEVCL		0x808629FB
@@@ -10840,149 -7810,6 +7811,6 @@@ enum skl_power_gate 
    						    PORTTC1_PLL_ENABLE, \
    						    PORTTC2_PLL_ENABLE)
- #define _MG_REFCLKIN_CTL_PORT1				0x16892C
- #define _MG_REFCLKIN_CTL_PORT2				0x16992C
- #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
- #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
- #define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)
- #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
- #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
- 					    _MG_REFCLKIN_CTL_PORT1, \
- 					    _MG_REFCLKIN_CTL_PORT2)
- 
- #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
- #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
- #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
- #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
- #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)		((x) << 16)
- #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
- #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
- #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
- #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
- 						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
- 						   _MG_CLKTOP2_CORECLKCTL1_PORT2)
- 
- #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
- #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
- #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
- #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
- #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)		((x) << 16)
- #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
- #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
- #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
- #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
- #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
- #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
- #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
- #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
- #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
- #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8
- #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
- #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
- 						_MG_CLKTOP2_HSCLKCTL_PORT1, \
- 						_MG_CLKTOP2_HSCLKCTL_PORT2)
- 
- #define _MG_PLL_DIV0_PORT1				0x168A00
- #define _MG_PLL_DIV0_PORT2				0x169A00
- #define _MG_PLL_DIV0_PORT3				0x16AA00
- #define _MG_PLL_DIV0_PORT4				0x16BA00
- #define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)
- #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
- #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT			8
- #define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)
- #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
- #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
- #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
- 					_MG_PLL_DIV0_PORT2)
- 
- #define _MG_PLL_DIV1_PORT1				0x168A04
- #define _MG_PLL_DIV1_PORT2				0x169A04
- #define _MG_PLL_DIV1_PORT3				0x16AA04
- #define _MG_PLL_DIV1_PORT4				0x16BA04
- #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)			((x) << 16)
- #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
- #define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)
- #define   MG_PLL_DIV1_DITHER_DIV_4			(2 << 12)
- #define   MG_PLL_DIV1_DITHER_DIV_8			(3 << 12)
- #define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)
- #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
- #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
- #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
- 					_MG_PLL_DIV1_PORT2)
- 
- #define _MG_PLL_LF_PORT1				0x168A08
- #define _MG_PLL_LF_PORT2				0x169A08
- #define _MG_PLL_LF_PORT3				0x16AA08
- #define _MG_PLL_LF_PORT4				0x16BA08
- #define   MG_PLL_LF_TDCTARGETCNT(x)			((x) << 24)
- #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
- #define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)
- #define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)
- #define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)
- #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
- #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
- 				      _MG_PLL_LF_PORT2)
- 
- #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
- #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
- #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
- #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
- #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)
- #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)
- #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)		((x) << 11)
- #define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)
- #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)
- #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
- #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
- 					     _MG_PLL_FRAC_LOCK_PORT1, \
- 					     _MG_PLL_FRAC_LOCK_PORT2)
- 
- #define _MG_PLL_SSC_PORT1				0x168A10
- #define _MG_PLL_SSC_PORT2				0x169A10
- #define _MG_PLL_SSC_PORT3				0x16AA10
- #define _MG_PLL_SSC_PORT4				0x16BA10
- #define   MG_PLL_SSC_EN					(1 << 28)
- #define   MG_PLL_SSC_TYPE(x)				((x) << 26)
- #define   MG_PLL_SSC_STEPLENGTH(x)			((x) << 16)
- #define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)
- #define   MG_PLL_SSC_FLLEN				(1 << 9)
- #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
- #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
- 				       _MG_PLL_SSC_PORT2)
- 
- #define _MG_PLL_BIAS_PORT1				0x168A14
- #define _MG_PLL_BIAS_PORT2				0x169A14
- #define _MG_PLL_BIAS_PORT3				0x16AA14
- #define _MG_PLL_BIAS_PORT4				0x16BA14
- #define   MG_PLL_BIAS_BIAS_GB_SEL(x)			((x) << 30)
- #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
- #define   MG_PLL_BIAS_INIT_DCOAMP(x)			((x) << 24)
- #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
- #define   MG_PLL_BIAS_BIAS_BONUS(x)			((x) << 16)
- #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
- #define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)
- #define   MG_PLL_BIAS_CTRIM(x)				((x) << 8)
- #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
- #define   MG_PLL_BIAS_VREF_RDAC(x)			((x) << 5)
- #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
- #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
- #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
- #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
- 					_MG_PLL_BIAS_PORT2)
- 
- #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
- #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
- #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
- #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
- #define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)
- #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)	((x) << 17)
- #define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)
- #define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)
- #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
- #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
- 						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
- 						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
- 
  #define _ICL_DPLL0_CFGCR0		0x164000
  #define _ICL_DPLL1_CFGCR0		0x164080
  #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
@@@ -11039,6 -7866,12 +7867,12 @@@
  #define RKL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
    					  _TGL_DPLL1_CFGCR0)
+ #define _TGL_DPLL0_DIV0					0x164B00
+ #define _TGL_DPLL1_DIV0					0x164C00
+ #define TGL_DPLL0_DIV0(pll)				_MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
+ #define   TGL_DPLL0_DIV0_AFC_STARTUP_MASK		REG_GENMASK(27, 25)
+ #define   TGL_DPLL0_DIV0_AFC_STARTUP(val)		REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
+ 
  #define _TGL_DPLL0_CFGCR1		0x164288
  #define _TGL_DPLL1_CFGCR1		0x164290
  #define _TGL_TBTPLL_CFGCR1		0x1642A0
@@@ -11085,7 -7918,15 +7919,15 @@@
  #define _DKL_PHY6_BASE			0x16D000
/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+ #define _DKL_PCS_DW5			0x14
+ #define DKL_PCS_DW5(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ 						    _DKL_PHY2_BASE) + \
+ 						    _DKL_PCS_DW5)
+ #define   DKL_PCS_DW5_CORE_SOFTRESET	REG_BIT(11)
+ 
  #define _DKL_PLL_DIV0			0x200
+ #define   DKL_PLL_DIV0_AFC_STARTUP_MASK	REG_GENMASK(27, 25)
+ #define   DKL_PLL_DIV0_AFC_STARTUP(val)	REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
  #define   DKL_PLL_DIV0_INTEG_COEFF(x)	((x) << 16)
  #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
  #define   DKL_PLL_DIV0_PROP_COEFF(x)	((x) << 12)
@@@ -11095,6 -7936,10 +7937,10 @@@
  #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
  #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
  #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
+ #define   DKL_PLL_DIV0_MASK		(DKL_PLL_DIV0_INTEG_COEFF_MASK | \
+ 					 DKL_PLL_DIV0_PROP_COEFF_MASK | \
+ 					 DKL_PLL_DIV0_FBPREDIV_MASK | \
+ 					 DKL_PLL_DIV0_FBDIV_INT_MASK)
  #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
    					    _DKL_PHY2_BASE) + \
    					    _DKL_PLL_DIV0)
@@@ -11268,93 -8113,7 +8114,7 @@@
  #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
  #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
- #define BXT_D_CR_DRP0_DUNIT8			0x1000
- #define BXT_D_CR_DRP0_DUNIT9			0x1200
- #define  BXT_D_CR_DRP0_DUNIT_START		8
- #define  BXT_D_CR_DRP0_DUNIT_END		11
- #define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
- 				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
- 						 BXT_D_CR_DRP0_DUNIT9))
- #define  BXT_DRAM_RANK_MASK			0x3
- #define  BXT_DRAM_RANK_SINGLE			0x1
- #define  BXT_DRAM_RANK_DUAL			0x3
- #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
- #define  BXT_DRAM_WIDTH_SHIFT			4
- #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
- #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
- #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
- #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
- #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
- #define  BXT_DRAM_SIZE_SHIFT			6
- #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
- #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
- #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
- #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
- #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
- #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
- #define  BXT_DRAM_TYPE_SHIFT			22
- #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
- #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
- #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
- #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
- 
- #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
- #define  DG1_GEAR_TYPE				REG_BIT(16)
- 
- #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
- #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
- #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
- #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
- #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
- #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
- 
- #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
- #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
- #define  SKL_DRAM_S_SHIFT			16
- #define  SKL_DRAM_SIZE_MASK			0x3F
- #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
- #define  SKL_DRAM_WIDTH_SHIFT			8
- #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
- #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
- #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
- #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
- #define  SKL_DRAM_RANK_SHIFT			10
- #define  SKL_DRAM_RANK_1			(0x0 << 10)
- #define  SKL_DRAM_RANK_2			(0x1 << 10)
- #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
- #define  ICL_DRAM_SIZE_MASK			0x7F
- #define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
- #define  ICL_DRAM_WIDTH_SHIFT			7
- #define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
- #define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
- #define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
- #define  ICL_DRAM_RANK_MASK			(0x3 << 9)
- #define  ICL_DRAM_RANK_SHIFT			9
- #define  ICL_DRAM_RANK_1			(0x0 << 9)
- #define  ICL_DRAM_RANK_2			(0x1 << 9)
- #define  ICL_DRAM_RANK_3			(0x2 << 9)
- #define  ICL_DRAM_RANK_4			(0x3 << 9)
- 
- #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
- #define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
- #define  DG1_QCLK_REFERENCE			REG_BIT(10)
- 
- #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
- #define   DG1_DRAM_T_RDPRE_MASK			REG_GENMASK(16, 11)
- #define   DG1_DRAM_T_RP_MASK			REG_GENMASK(6, 0)
- #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
- #define   DG1_DRAM_T_RCD_MASK			REG_GENMASK(15, 9)
- #define   DG1_DRAM_T_RAS_MASK			REG_GENMASK(8, 1)
- 
- /*
-  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
-  * since on HSW we can't write to it using intel_uncore_write.
-  */
- #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
  #define D_COMP_BDW			_MMIO(0x138144)
- #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
- #define  D_COMP_COMP_FORCE		(1 << 8)
- #define  D_COMP_COMP_DISABLE		(1 << 0)
/* Pipe WM_LINETIME - watermark line time */
  #define _WM_LINETIME_A		0x45270
@@@ -11644,93 -8403,6 +8404,6 @@@
  #define CGM_PIPE_GAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
  #define CGM_PIPE_MODE(pipe)		_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
- /* MIPI DSI registers */
- 
- #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
- #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
- 
- /* Gen11 DSI */
- #define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
- 						    dsi0, dsi1)
- 
- #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
- #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
- #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
- #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
- 
- #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
- #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
- #define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
- 							_ICL_DSI_ESC_CLK_DIV0, \
- 							_ICL_DSI_ESC_CLK_DIV1)
- #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
- #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
- #define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
- 						_ICL_DPHY_ESC_CLK_DIV0, \
- 						_ICL_DPHY_ESC_CLK_DIV1)
- #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
- #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
- #define  ICL_ESC_CLK_DIV_MASK			0x1ff
- #define  ICL_ESC_CLK_DIV_SHIFT			0
- #define DSI_MAX_ESC_CLK			20000		/* in KHz */
- 
- #define _ADL_MIPIO_REG			0x180
- #define ADL_MIPIO_DW(port, dw)		_MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
- #define   TX_ESC_CLK_DIV_PHY_SEL	REGBIT(16)
- #define   TX_ESC_CLK_DIV_PHY_MASK	REG_GENMASK(23, 16)
- #define   TX_ESC_CLK_DIV_PHY		REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
- 
- #define _DSI_CMD_FRMCTL_0		0x6b034
- #define _DSI_CMD_FRMCTL_1		0x6b834
- #define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
- 						   _DSI_CMD_FRMCTL_0,\
- 						   _DSI_CMD_FRMCTL_1)
- #define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
- #define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
- #define   DSI_NULL_PACKET_ENABLE		(1 << 28)
- #define   DSI_FRAME_IN_PROGRESS			(1 << 0)
- 
- #define _DSI_INTR_MASK_REG_0		0x6b070
- #define _DSI_INTR_MASK_REG_1		0x6b870
- #define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
- 						   _DSI_INTR_MASK_REG_0,\
- 						   _DSI_INTR_MASK_REG_1)
- 
- #define _DSI_INTR_IDENT_REG_0		0x6b074
- #define _DSI_INTR_IDENT_REG_1		0x6b874
- #define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
- 						   _DSI_INTR_IDENT_REG_0,\
- 						   _DSI_INTR_IDENT_REG_1)
- #define   DSI_TE_EVENT				(1 << 31)
- #define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
- #define   DSI_TX_DATA				(1 << 29)
- #define   DSI_ULPS_ENTRY_DONE			(1 << 28)
- #define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
- #define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
- #define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
- #define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
- #define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
- #define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
- #define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
- #define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
- #define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
- #define   DSI_FRAME_UPDATE_DONE			(1 << 16)
- #define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
- #define   DSI_INVALID_TX_LENGTH			(1 << 13)
- #define   DSI_INVALID_VC			(1 << 12)
- #define   DSI_INVALID_DATA_TYPE			(1 << 11)
- #define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
- #define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
- #define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
- #define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
- #define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
- #define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
- #define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
- #define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
- #define   DSI_EOT_SYNC_ERROR			(1 << 2)
- #define   DSI_SOT_SYNC_ERROR			(1 << 1)
- #define   DSI_SOT_ERROR				(1 << 0)
- 
  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
  #define GEN4_TIMESTAMP		_MMIO(0x2358)
  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
@@@ -11746,143 -8418,6 +8419,6 @@@
  #define PIPE_FRMTMSTMP(pipe)		\
    		_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
- /* BXT MIPI clock controls */
- #define BXT_MAX_VAR_OUTPUT_KHZ			39500
- 
- #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
- #define  BXT_MIPI1_DIV_SHIFT			26
- #define  BXT_MIPI2_DIV_SHIFT			10
- #define  BXT_MIPI_DIV_SHIFT(port)		\
- 			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
- 					BXT_MIPI2_DIV_SHIFT)
- 
- /* TX control divider to select actual TX clock output from (8x/var) */
- #define  BXT_MIPI1_TX_ESCLK_SHIFT		26
- #define  BXT_MIPI2_TX_ESCLK_SHIFT		10
- #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
- 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
- 					BXT_MIPI2_TX_ESCLK_SHIFT)
- #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
- #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
- #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
- 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
- 					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
- #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
- 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
- /* RX upper control divider to select actual RX clock output from 8x */
- #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
- #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
- #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
- 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
- 					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
- #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
- #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
- #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
- 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
- 					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
- #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
- 		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
- /* 8/3X divider to select the actual 8/3X clock output from 8x */
- #define  BXT_MIPI1_8X_BY3_SHIFT                19
- #define  BXT_MIPI2_8X_BY3_SHIFT                3
- #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
- 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
- 					BXT_MIPI2_8X_BY3_SHIFT)
- #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
- #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
- #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
- 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
- 						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
- #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
- 			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
- /* RX lower control divider to select actual RX clock output from 8x */
- #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
- #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
- #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
- 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
- 					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
- #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
- #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
- #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
- 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
- 					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
- #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
- 		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
- 
- #define RX_DIVIDER_BIT_1_2                     0x3
- #define RX_DIVIDER_BIT_3_4                     0xC
- 
- /* BXT MIPI mode configure */
- #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
- #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
- #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
- 		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
- 
- #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
- #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
- #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
- 		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
- 
- #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
- #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
- #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
- 		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
- 
- #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
- #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
- #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
- #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
- #define  BXT_DSIC_16X_BY1		(0 << 10)
- #define  BXT_DSIC_16X_BY2		(1 << 10)
- #define  BXT_DSIC_16X_BY3		(2 << 10)
- #define  BXT_DSIC_16X_BY4		(3 << 10)
- #define  BXT_DSIC_16X_MASK		(3 << 10)
- #define  BXT_DSIA_16X_BY1		(0 << 8)
- #define  BXT_DSIA_16X_BY2		(1 << 8)
- #define  BXT_DSIA_16X_BY3		(2 << 8)
- #define  BXT_DSIA_16X_BY4		(3 << 8)
- #define  BXT_DSIA_16X_MASK		(3 << 8)
- #define  BXT_DSI_FREQ_SEL_SHIFT		8
- #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
- 
- #define BXT_DSI_PLL_RATIO_MAX		0x7D
- #define BXT_DSI_PLL_RATIO_MIN		0x22
- #define GLK_DSI_PLL_RATIO_MAX		0x6F
- #define GLK_DSI_PLL_RATIO_MIN		0x22
- #define BXT_DSI_PLL_RATIO_MASK		0xFF
- #define BXT_REF_CLOCK_KHZ		19200
- 
- #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
- #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
- #define  BXT_DSI_PLL_LOCKED		(1 << 30)
- 
- #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
- #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
- #define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
- 
-  /* BXT port control */
- #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
- #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
- #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
- 
- /* ICL DSI MODE control */
- #define _ICL_DSI_IO_MODECTL_0				0x6B094
- #define _ICL_DSI_IO_MODECTL_1				0x6B894
- #define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
- 						    _ICL_DSI_IO_MODECTL_0, \
- 						    _ICL_DSI_IO_MODECTL_1)
- #define  COMBO_PHY_MODE_DSI				(1 << 0)
- 
- /* TGL DSI Chicken register */
- #define _TGL_DSI_CHKN_REG_0			0x6B0C0
- #define _TGL_DSI_CHKN_REG_1			0x6B8C0
- #define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\
- 						    _TGL_DSI_CHKN_REG_0, \
- 						    _TGL_DSI_CHKN_REG_1)
- #define TGL_DSI_CHKN_LSHS_GB_MASK		REG_GENMASK(15, 12)
- #define TGL_DSI_CHKN_LSHS_GB(byte_clocks)	REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
- 							       (byte_clocks))
- 
  /* Display Stream Splitter Control */
  #define DSS_CTL1				_MMIO(0x67400)
  #define  SPLITTER_ENABLE			(1 << 31)
@@@ -11921,718 -8456,6 +8457,6 @@@
    						   _ICL_PIPE_DSS_CTL2_PB, \
    						   _ICL_PIPE_DSS_CTL2_PC)
- #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
- #define  STAP_SELECT					(1 << 0)
- 
- #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
- #define  HS_IO_CTRL_SELECT				(1 << 0)
- 
- #define  DPI_ENABLE					(1 << 31) /* A + C */
- #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
- #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
- #define  DUAL_LINK_MODE_SHIFT				26
- #define  DUAL_LINK_MODE_MASK				(1 << 26)
- #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
- #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
- #define  DITHERING_ENABLE				(1 << 25) /* A + C */
- #define  FLOPPED_HSTX					(1 << 23)
- #define  DE_INVERT					(1 << 19) /* XXX */
- #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
- #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
- #define  AFE_LATCHOUT					(1 << 17)
- #define  LP_OUTPUT_HOLD					(1 << 16)
- #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
- #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
- #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
- #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
- #define  CSB_SHIFT					9
- #define  CSB_MASK					(3 << 9)
- #define  CSB_20MHZ					(0 << 9)
- #define  CSB_10MHZ					(1 << 9)
- #define  CSB_40MHZ					(2 << 9)
- #define  BANDGAP_MASK					(1 << 8)
- #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
- #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
- #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
- #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
- #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
- #define  TEARING_EFFECT_SHIFT				2 /* A + C */
- #define  TEARING_EFFECT_MASK				(3 << 2)
- #define  TEARING_EFFECT_OFF				(0 << 2)
- #define  TEARING_EFFECT_DSI				(1 << 2)
- #define  TEARING_EFFECT_GPIO				(2 << 2)
- #define  LANE_CONFIGURATION_SHIFT			0
- #define  LANE_CONFIGURATION_MASK			(3 << 0)
- #define  LANE_CONFIGURATION_4LANE			(0 << 0)
- #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
- #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
- 
- #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
- #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
- #define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
- #define  TEARING_EFFECT_DELAY_SHIFT			0
- #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
- 
- /* XXX: all bits reserved */
- #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
- 
- /* MIPI DSI Controller and D-PHY registers */
- 
- #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
- #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
- #define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
- #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
- #define  ULPS_STATE_MASK				(3 << 1)
- #define  ULPS_STATE_ENTER				(2 << 1)
- #define  ULPS_STATE_EXIT				(1 << 1)
- #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
- #define  DEVICE_READY					(1 << 0)
- 
- #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
- #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
- #define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
- #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
- #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
- #define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
- #define  TEARING_EFFECT					(1 << 31)
- #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
- #define  GEN_READ_DATA_AVAIL				(1 << 29)
- #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
- #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
- #define  RX_PROT_VIOLATION				(1 << 26)
- #define  RX_INVALID_TX_LENGTH				(1 << 25)
- #define  ACK_WITH_NO_ERROR				(1 << 24)
- #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
- #define  LP_RX_TIMEOUT					(1 << 22)
- #define  HS_TX_TIMEOUT					(1 << 21)
- #define  DPI_FIFO_UNDERRUN				(1 << 20)
- #define  LOW_CONTENTION					(1 << 19)
- #define  HIGH_CONTENTION				(1 << 18)
- #define  TXDSI_VC_ID_INVALID				(1 << 17)
- #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
- #define  TXCHECKSUM_ERROR				(1 << 15)
- #define  TXECC_MULTIBIT_ERROR				(1 << 14)
- #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
- #define  TXFALSE_CONTROL_ERROR				(1 << 12)
- #define  RXDSI_VC_ID_INVALID				(1 << 11)
- #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
- #define  RXCHECKSUM_ERROR				(1 << 9)
- #define  RXECC_MULTIBIT_ERROR				(1 << 8)
- #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
- #define  RXFALSE_CONTROL_ERROR				(1 << 6)
- #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
- #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
- #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
- #define  RXEOT_SYNC_ERROR				(1 << 2)
- #define  RXSOT_SYNC_ERROR				(1 << 1)
- #define  RXSOT_ERROR					(1 << 0)
- 
- #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
- #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
- #define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
- #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
- #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
- #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
- #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
- #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
- #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
- #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
- #define  VID_MODE_FORMAT_MASK				(0xf << 7)
- #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
- #define  VID_MODE_FORMAT_RGB565				(1 << 7)
- #define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
- #define  VID_MODE_FORMAT_RGB666				(3 << 7)
- #define  VID_MODE_FORMAT_RGB888				(4 << 7)
- #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
- #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
- #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
- #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
- #define  DATA_LANES_PRG_REG_SHIFT			0
- #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
- 
- #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
- #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
- #define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
- #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
- 
- #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
- #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
- #define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
- #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
- 
- #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
- #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
- #define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
- #define  TURN_AROUND_TIMEOUT_MASK			0x3f
- 
- #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
- #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
- #define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
- #define  DEVICE_RESET_TIMER_MASK			0xffff
- 
- #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
- #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
- #define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
- #define  VERTICAL_ADDRESS_SHIFT				16
- #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
- #define  HORIZONTAL_ADDRESS_SHIFT			0
- #define  HORIZONTAL_ADDRESS_MASK			0xffff
- 
- #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
- #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
- #define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
- #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
- #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
- #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
- 
- /* regs below are bits 15:0 */
- #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
- #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
- #define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
- 
- #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
- #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
- #define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
- 
- #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
- #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
- #define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
- 
- #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
- #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
- #define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
- 
- #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
- #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
- #define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
- 
- #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
- #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
- #define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
- 
- #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
- #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
- #define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
- 
- #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
- #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
- #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
- 
- /* regs above are bits 15:0 */
- 
- #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
- #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
- #define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
- #define  DPI_LP_MODE					(1 << 6)
- #define  BACKLIGHT_OFF					(1 << 5)
- #define  BACKLIGHT_ON					(1 << 4)
- #define  COLOR_MODE_OFF					(1 << 3)
- #define  COLOR_MODE_ON					(1 << 2)
- #define  TURN_ON					(1 << 1)
- #define  SHUTDOWN					(1 << 0)
- 
- #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
- #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
- #define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
- #define  COMMAND_BYTE_SHIFT				0
- #define  COMMAND_BYTE_MASK				(0x3f << 0)
- 
- #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
- #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
- #define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
- #define  MASTER_INIT_TIMER_SHIFT			0
- #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
- 
- #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
- #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
- #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
- 			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
- #define  MAX_RETURN_PKT_SIZE_SHIFT			0
- #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
- 
- #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
- #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
- #define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
- #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
- #define  DISABLE_VIDEO_BTA				(1 << 3)
- #define  IP_TG_CONFIG					(1 << 2)
- #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
- #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
- #define  VIDEO_MODE_BURST				(3 << 0)
- 
- #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
- #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
- #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
- #define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
- #define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
- #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
- #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
- #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
- #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
- #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
- #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
- #define  CLOCKSTOP					(1 << 1)
- #define  EOT_DISABLE					(1 << 0)
- 
- #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
- #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
- #define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
- #define  LP_BYTECLK_SHIFT				0
- #define  LP_BYTECLK_MASK				(0xffff << 0)
- 
- #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
- #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
- #define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
- 
- #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
- #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
- #define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
- 
- /* bits 31:0 */
- #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
- #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
- #define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
- 
- /* bits 31:0 */
- #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
- #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
- #define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
- 
- #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
- #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
- #define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
- #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
- #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
- #define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
- #define  LONG_PACKET_WORD_COUNT_SHIFT			8
- #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
- #define  SHORT_PACKET_PARAM_SHIFT			8
- #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
- #define  VIRTUAL_CHANNEL_SHIFT				6
- #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
- #define  DATA_TYPE_SHIFT				0
- #define  DATA_TYPE_MASK					(0x3f << 0)
- /* data type values, see include/video/mipi_display.h */
- 
- #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
- #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
- #define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
- #define  DPI_FIFO_EMPTY					(1 << 28)
- #define  DBI_FIFO_EMPTY					(1 << 27)
- #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
- #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
- #define  LP_CTRL_FIFO_FULL				(1 << 24)
- #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
- #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
- #define  HS_CTRL_FIFO_FULL				(1 << 16)
- #define  LP_DATA_FIFO_EMPTY				(1 << 10)
- #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
- #define  LP_DATA_FIFO_FULL				(1 << 8)
- #define  HS_DATA_FIFO_EMPTY				(1 << 2)
- #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
- #define  HS_DATA_FIFO_FULL				(1 << 0)
- 
- #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
- #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
- #define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
- #define  DBI_HS_LP_MODE_MASK				(1 << 0)
- #define  DBI_LP_MODE					(1 << 0)
- #define  DBI_HS_MODE					(0 << 0)
- 
- #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
- #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
- #define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
- #define  EXIT_ZERO_COUNT_SHIFT				24
- #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
- #define  TRAIL_COUNT_SHIFT				16
- #define  TRAIL_COUNT_MASK				(0x1f << 16)
- #define  CLK_ZERO_COUNT_SHIFT				8
- #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
- #define  PREPARE_COUNT_SHIFT				0
- #define  PREPARE_COUNT_MASK				(0x3f << 0)
- 
- #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
- #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
- #define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
- 						   _ICL_DSI_T_INIT_MASTER_0,\
- 						   _ICL_DSI_T_INIT_MASTER_1)
- 
- #define _DPHY_CLK_TIMING_PARAM_0	0x162180
- #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
- #define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DPHY_CLK_TIMING_PARAM_0,\
- 						   _DPHY_CLK_TIMING_PARAM_1)
- #define _DSI_CLK_TIMING_PARAM_0		0x6b080
- #define _DSI_CLK_TIMING_PARAM_1		0x6b880
- #define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DSI_CLK_TIMING_PARAM_0,\
- 						   _DSI_CLK_TIMING_PARAM_1)
- #define  CLK_PREPARE_OVERRIDE		(1 << 31)
- #define  CLK_PREPARE(x)		((x) << 28)
- #define  CLK_PREPARE_MASK		(0x7 << 28)
- #define  CLK_PREPARE_SHIFT		28
- #define  CLK_ZERO_OVERRIDE		(1 << 27)
- #define  CLK_ZERO(x)			((x) << 20)
- #define  CLK_ZERO_MASK			(0xf << 20)
- #define  CLK_ZERO_SHIFT		20
- #define  CLK_PRE_OVERRIDE		(1 << 19)
- #define  CLK_PRE(x)			((x) << 16)
- #define  CLK_PRE_MASK			(0x3 << 16)
- #define  CLK_PRE_SHIFT			16
- #define  CLK_POST_OVERRIDE		(1 << 15)
- #define  CLK_POST(x)			((x) << 8)
- #define  CLK_POST_MASK			(0x7 << 8)
- #define  CLK_POST_SHIFT		8
- #define  CLK_TRAIL_OVERRIDE		(1 << 7)
- #define  CLK_TRAIL(x)			((x) << 0)
- #define  CLK_TRAIL_MASK		(0xf << 0)
- #define  CLK_TRAIL_SHIFT		0
- 
- #define _DPHY_DATA_TIMING_PARAM_0	0x162184
- #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
- #define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DPHY_DATA_TIMING_PARAM_0,\
- 						   _DPHY_DATA_TIMING_PARAM_1)
- #define _DSI_DATA_TIMING_PARAM_0	0x6B084
- #define _DSI_DATA_TIMING_PARAM_1	0x6B884
- #define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DSI_DATA_TIMING_PARAM_0,\
- 						   _DSI_DATA_TIMING_PARAM_1)
- #define  HS_PREPARE_OVERRIDE		(1 << 31)
- #define  HS_PREPARE(x)			((x) << 24)
- #define  HS_PREPARE_MASK		(0x7 << 24)
- #define  HS_PREPARE_SHIFT		24
- #define  HS_ZERO_OVERRIDE		(1 << 23)
- #define  HS_ZERO(x)			((x) << 16)
- #define  HS_ZERO_MASK			(0xf << 16)
- #define  HS_ZERO_SHIFT			16
- #define  HS_TRAIL_OVERRIDE		(1 << 15)
- #define  HS_TRAIL(x)			((x) << 8)
- #define  HS_TRAIL_MASK			(0x7 << 8)
- #define  HS_TRAIL_SHIFT		8
- #define  HS_EXIT_OVERRIDE		(1 << 7)
- #define  HS_EXIT(x)			((x) << 0)
- #define  HS_EXIT_MASK			(0x7 << 0)
- #define  HS_EXIT_SHIFT			0
- 
- #define _DPHY_TA_TIMING_PARAM_0		0x162188
- #define _DPHY_TA_TIMING_PARAM_1		0x6c188
- #define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DPHY_TA_TIMING_PARAM_0,\
- 						   _DPHY_TA_TIMING_PARAM_1)
- #define _DSI_TA_TIMING_PARAM_0		0x6b098
- #define _DSI_TA_TIMING_PARAM_1		0x6b898
- #define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
- 						   _DSI_TA_TIMING_PARAM_0,\
- 						   _DSI_TA_TIMING_PARAM_1)
- #define  TA_SURE_OVERRIDE		(1 << 31)
- #define  TA_SURE(x)			((x) << 16)
- #define  TA_SURE_MASK			(0x1f << 16)
- #define  TA_SURE_SHIFT			16
- #define  TA_GO_OVERRIDE		(1 << 15)
- #define  TA_GO(x)			((x) << 8)
- #define  TA_GO_MASK			(0xf << 8)
- #define  TA_GO_SHIFT			8
- #define  TA_GET_OVERRIDE		(1 << 7)
- #define  TA_GET(x)			((x) << 0)
- #define  TA_GET_MASK			(0xf << 0)
- #define  TA_GET_SHIFT			0
- 
- /* DSI transcoder configuration */
- #define _DSI_TRANS_FUNC_CONF_0		0x6b030
- #define _DSI_TRANS_FUNC_CONF_1		0x6b830
- #define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_TRANS_FUNC_CONF_0,\
- 						  _DSI_TRANS_FUNC_CONF_1)
- #define  OP_MODE_MASK			(0x3 << 28)
- #define  OP_MODE_SHIFT			28
- #define  CMD_MODE_NO_GATE		(0x0 << 28)
- #define  CMD_MODE_TE_GATE		(0x1 << 28)
- #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
- #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
- #define  TE_SOURCE_GPIO			(1 << 27)
- #define  LINK_READY			(1 << 20)
- #define  PIX_FMT_MASK			(0x3 << 16)
- #define  PIX_FMT_SHIFT			16
- #define  PIX_FMT_RGB565			(0x0 << 16)
- #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
- #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
- #define  PIX_FMT_RGB888			(0x3 << 16)
- #define  PIX_FMT_RGB101010		(0x4 << 16)
- #define  PIX_FMT_RGB121212		(0x5 << 16)
- #define  PIX_FMT_COMPRESSED		(0x6 << 16)
- #define  BGR_TRANSMISSION		(1 << 15)
- #define  PIX_VIRT_CHAN(x)		((x) << 12)
- #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
- #define  PIX_VIRT_CHAN_SHIFT		12
- #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
- #define  PIX_BUF_THRESHOLD_SHIFT	10
- #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
- #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
- #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
- #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
- #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
- #define  CONTINUOUS_CLK_SHIFT		8
- #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
- #define  CLK_HS_OR_LP			(0x2 << 8)
- #define  CLK_HS_CONTINUOUS		(0x3 << 8)
- #define  LINK_CALIBRATION_MASK		(0x3 << 4)
- #define  LINK_CALIBRATION_SHIFT		4
- #define  CALIBRATION_DISABLED		(0x0 << 4)
- #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
- #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
- #define  BLANKING_PACKET_ENABLE		(1 << 2)
- #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
- #define  EOTP_DISABLED			(1 << 0)
- 
- #define _DSI_CMD_RXCTL_0		0x6b0d4
- #define _DSI_CMD_RXCTL_1		0x6b8d4
- #define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_CMD_RXCTL_0,\
- 						  _DSI_CMD_RXCTL_1)
- #define  READ_UNLOADS_DW		(1 << 16)
- #define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
- #define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
- #define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
- #define  RECEIVED_RESET_TRIGGER		(1 << 12)
- #define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
- #define  RECEIVED_CRC_WAS_LOST		(1 << 10)
- #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
- #define  NUMBER_RX_PLOAD_DW_SHIFT	0
- 
- #define _DSI_CMD_TXCTL_0		0x6b0d0
- #define _DSI_CMD_TXCTL_1		0x6b8d0
- #define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_CMD_TXCTL_0,\
- 						  _DSI_CMD_TXCTL_1)
- #define  KEEP_LINK_IN_HS		(1 << 24)
- #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
- #define  FREE_HEADER_CREDIT_SHIFT	0x8
- #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
- #define  FREE_PLOAD_CREDIT_SHIFT	0
- #define  MAX_HEADER_CREDIT		0x10
- #define  MAX_PLOAD_CREDIT		0x40
- 
- #define _DSI_CMD_TXHDR_0		0x6b100
- #define _DSI_CMD_TXHDR_1		0x6b900
- #define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_CMD_TXHDR_0,\
- 						  _DSI_CMD_TXHDR_1)
- #define  PAYLOAD_PRESENT		(1 << 31)
- #define  LP_DATA_TRANSFER		(1 << 30)
- #define  VBLANK_FENCE			(1 << 29)
- #define  PARAM_WC_MASK			(0xffff << 8)
- #define  PARAM_WC_LOWER_SHIFT		8
- #define  PARAM_WC_UPPER_SHIFT		16
- #define  VC_MASK			(0x3 << 6)
- #define  VC_SHIFT			6
- #define  DT_MASK			(0x3f << 0)
- #define  DT_SHIFT			0
- 
- #define _DSI_CMD_TXPYLD_0		0x6b104
- #define _DSI_CMD_TXPYLD_1		0x6b904
- #define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_CMD_TXPYLD_0,\
- 						  _DSI_CMD_TXPYLD_1)
- 
- #define _DSI_LP_MSG_0			0x6b0d8
- #define _DSI_LP_MSG_1			0x6b8d8
- #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
- 						  _DSI_LP_MSG_0,\
- 						  _DSI_LP_MSG_1)
- #define  LPTX_IN_PROGRESS		(1 << 17)
- #define  LINK_IN_ULPS			(1 << 16)
- #define  LINK_ULPS_TYPE_LP11		(1 << 8)
- #define  LINK_ENTER_ULPS		(1 << 0)
- 
- /* DSI timeout registers */
- #define _DSI_HSTX_TO_0			0x6b044
- #define _DSI_HSTX_TO_1			0x6b844
- #define DSI_HSTX_TO(tc)			_MMIO_DSI(tc,	\
- 						  _DSI_HSTX_TO_0,\
- 						  _DSI_HSTX_TO_1)
- #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
- #define  HSTX_TIMEOUT_VALUE_SHIFT	16
- #define  HSTX_TIMEOUT_VALUE(x)		((x) << 16)
- #define  HSTX_TIMED_OUT			(1 << 0)
- 
- #define _DSI_LPRX_HOST_TO_0		0x6b048
- #define _DSI_LPRX_HOST_TO_1		0x6b848
- #define DSI_LPRX_HOST_TO(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_LPRX_HOST_TO_0,\
- 						  _DSI_LPRX_HOST_TO_1)
- #define  LPRX_TIMED_OUT			(1 << 16)
- #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
- #define  LPRX_TIMEOUT_VALUE_SHIFT	0
- #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
- 
- #define _DSI_PWAIT_TO_0			0x6b040
- #define _DSI_PWAIT_TO_1			0x6b840
- #define DSI_PWAIT_TO(tc)		_MMIO_DSI(tc,	\
- 						  _DSI_PWAIT_TO_0,\
- 						  _DSI_PWAIT_TO_1)
- #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
- #define  PRESET_TIMEOUT_VALUE_SHIFT	16
- #define  PRESET_TIMEOUT_VALUE(x)	((x) << 16)
- #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
- #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
- #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
- 
- #define _DSI_TA_TO_0			0x6b04c
- #define _DSI_TA_TO_1			0x6b84c
- #define DSI_TA_TO(tc)			_MMIO_DSI(tc,	\
- 						  _DSI_TA_TO_0,\
- 						  _DSI_TA_TO_1)
- #define  TA_TIMED_OUT			(1 << 16)
- #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
- #define  TA_TIMEOUT_VALUE_SHIFT		0
- #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
- 
- /* bits 31:0 */
- #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
- #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
- #define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
- 
- #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
- #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
- #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
- #define  LP_HS_SSW_CNT_SHIFT				16
- #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
- #define  HS_LP_PWR_SW_CNT_SHIFT				0
- #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
- 
- #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
- #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
- #define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
- #define  STOP_STATE_STALL_COUNTER_SHIFT			0
- #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
- 
- #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
- #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
- #define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
- #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
- #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
- #define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
- #define  RX_CONTENTION_DETECTED				(1 << 0)
- 
- /* XXX: only pipe A ?!? */
- #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
- #define  DBI_TYPEC_ENABLE				(1 << 31)
- #define  DBI_TYPEC_WIP					(1 << 30)
- #define  DBI_TYPEC_OPTION_SHIFT				28
- #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
- #define  DBI_TYPEC_FREQ_SHIFT				24
- #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
- #define  DBI_TYPEC_OVERRIDE				(1 << 8)
- #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
- #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
- 
- 
- /* MIPI adapter registers */
- 
- #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
- #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
- #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
- #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
- #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
- #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
- #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
- #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
- #define  READ_REQUEST_PRIORITY_SHIFT			3
- #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
- #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
- #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
- #define  RGB_FLIP_TO_BGR				(1 << 2)
- 
- #define  BXT_PIPE_SELECT_SHIFT				7
- #define  BXT_PIPE_SELECT_MASK				(7 << 7)
- #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
- #define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
- #define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
- #define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
- #define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
- #define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
- #define  GLK_LP_WAKE					(1 << 22)
- #define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
- #define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
- #define  GLK_FIREWALL_ENABLE				(1 << 16)
- #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
- #define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
- #define  BXT_DSC_ENABLE					(1 << 3)
- #define  BXT_RGB_FLIP					(1 << 2)
- #define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
- #define  GLK_MIPIIO_ENABLE				(1 << 0)
- 
- #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
- #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
- #define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
- #define  DATA_MEM_ADDRESS_SHIFT				5
- #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
- #define  DATA_VALID					(1 << 0)
- 
- #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
- #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
- #define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
- #define  DATA_LENGTH_SHIFT				0
- #define  DATA_LENGTH_MASK				(0xfffff << 0)
- 
- #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
- #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
- #define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
- #define  COMMAND_MEM_ADDRESS_SHIFT			5
- #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
- #define  AUTO_PWG_ENABLE				(1 << 2)
- #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
- #define  COMMAND_VALID					(1 << 0)
- 
- #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
- #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
- #define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
- #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
- #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
- 
- #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
- #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
- #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
- 
- #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
- #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
- #define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
- #define  READ_DATA_VALID(n)				(1 << (n))
- 
- /* MOCS (Memory Object Control State) registers */
- #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
- #define GEN9_LNCFCMOCS_REG_COUNT	32
- 
- #define __GEN9_RCS0_MOCS0	0xc800
- #define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
- #define __GEN9_VCS0_MOCS0	0xc900
- #define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
- #define __GEN9_VCS1_MOCS0	0xca00
- #define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
- #define __GEN9_VECS0_MOCS0	0xcb00
- #define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
- #define __GEN9_BCS0_MOCS0	0xcc00
- #define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
- #define __GEN11_VCS2_MOCS0	0x10000
- #define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
- 
- #define GEN9_SCRATCH_LNCF1		_MMIO(0xb008)
- #define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
- 
- #define GEN9_SCRATCH1			_MMIO(0xb11c)
- #define   EVICTION_PERF_FIX_ENABLE	REG_BIT(8)
- 
- #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
- #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
- #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
- #define   PMFLUSHDONE_LNEBLK		(1 << 22)
- 
- #define XEHP_L3NODEARBCFG		_MMIO(0xb0b4)
- #define   XEHP_LNESPARE			REG_BIT(19)
- 
- #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
- 
  #define GEN12_GSMBASE			_MMIO(0x108100)
  #define GEN12_DSMBASE			_MMIO(0x1080C0)
@@@ -12641,6 -8464,9 +8465,9 @@@
  #define   SGGI_DIS			REG_BIT(15)
  #define   SGR_DIS			REG_BIT(13)
+ #define XEHPSDV_FLAT_CCS_BASE_ADDR	_MMIO(0x4910)
+ #define   XEHPSDV_CCS_BASE_SHIFT	8
+ 
  /* gamt regs */
  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
@@@ -12654,8 -8480,10 +8481,10 @@@
#define _ICL_PHY_MISC_A		0x64C00
  #define _ICL_PHY_MISC_B		0x64C04
- #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
- 						 _ICL_PHY_MISC_B)
+ #define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+ #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+ #define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+ 				 ICL_PHY_MISC(port))
  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
@@@ -12995,6 -8823,14 +8824,14 @@@
  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
  #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
+ #define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
+ #define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
+ #define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
+ #define SPI_STATIC_REGIONS			_MMIO(0x102090)
+ #define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
+ #define OROM_OFFSET				_MMIO(0x1020c0)
+ #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
+ 
  /* This register controls the Display State Buffer (DSB) engines. */
  #define _DSBSL_INSTANCE_BASE		0x70B00
  #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
@@@ -13005,19 -8841,14 +8842,14 @@@
  #define   DSB_ENABLE			(1 << 31)
  #define   DSB_STATUS			(1 << 0)
- #define TGL_ROOT_DEVICE_ID		0x9A00
- #define TGL_ROOT_DEVICE_MASK		0xFF00
- #define TGL_ROOT_DEVICE_SKU_MASK	0xF
- #define TGL_ROOT_DEVICE_SKU_ULX		0x2
- #define TGL_ROOT_DEVICE_SKU_ULT		0x4
- 
  #define CLKREQ_POLICY			_MMIO(0x101038)
  #define  CLKREQ_POLICY_MEM_UP_OVRD	REG_BIT(1)
#define CLKGATE_DIS_MISC			_MMIO(0x46534)
  #define  CLKGATE_DIS_MISC_DMASC_GATING_DIS	REG_BIT(21)
- #define SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731C)
- #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
+ #define GEN12_CULLBIT1			_MMIO(0x6100)
+ #define GEN12_CULLBIT2			_MMIO(0x7030)
+ #define GEN12_STATE_ACK_DEBUG		_MMIO(0x20BC)
#endif /* _I915_REG_H_ */
diff --combined drivers/gpu/drm/i915/intel_pch.c
index fc8a68f3a2ed,4f7a61d5502e..4cce044efde2
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@@ -108,7 -108,6 +108,7 @@@ intel_pch_type(const struct drm_i915_pr
    	/* Comet Lake V PCH is based on KBP, which is SPT compatible */
    	return PCH_SPT;
    case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 +	case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
    	drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n");
    	drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
    	return PCH_ICP;
@@@ -124,12 -123,14 +124,13 @@@
    		    !IS_GEN9_BC(dev_priv));
    	return PCH_TGP;
    case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 -	case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
    	drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
    	drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
    	return PCH_JSP;
    case INTEL_PCH_ADP_DEVICE_ID_TYPE:
    case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
    case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
+ 	case INTEL_PCH_ADP4_DEVICE_ID_TYPE:
    	drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
    	drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
    		    !IS_ALDERLAKE_P(dev_priv));
diff --combined drivers/gpu/drm/i915/intel_pch.h
index 4ba0f1967cca,6fd20408f7bf..b7a8cf409d48
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@@ -50,14 -50,15 +50,15 @@@ enum intel_pch 
  #define INTEL_PCH_CMP2_DEVICE_ID_TYPE		0x0680
  #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE		0xA380
  #define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
 +#define INTEL_PCH_ICP2_DEVICE_ID_TYPE		0x3880
  #define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
  #define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
  #define INTEL_PCH_TGP2_DEVICE_ID_TYPE		0x4380
  #define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80
 -#define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880
  #define INTEL_PCH_ADP_DEVICE_ID_TYPE		0x7A80
  #define INTEL_PCH_ADP2_DEVICE_ID_TYPE		0x5180
  #define INTEL_PCH_ADP3_DEVICE_ID_TYPE		0x7A00
+ #define INTEL_PCH_ADP4_DEVICE_ID_TYPE		0x5480
  #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
  #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
diff --combined drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 188c94cc08a5,8cc0a1283d7c..ede435d2c1ef
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@@ -12,6 -12,7 +12,6 @@@
  #include <linux/soc/mediatek/mtk-mutex.h>
#include <asm/barrier.h>
 -#include <soc/mediatek/smi.h>
#include <drm/drm_atomic.h>
  #include <drm/drm_atomic_helper.h>
@@@ -55,6 -56,7 +55,7 @@@ struct mtk_drm_crtc 
    struct cmdq_pkt			cmdq_handle;
    u32				cmdq_event;
    u32				cmdq_vblank_cnt;
+ 	wait_queue_head_t		cb_blocking_queue;
  #endif
struct device			*mmsys_dev;
@@@ -313,6 -315,7 +314,7 @@@ static void ddp_cmdq_cb(struct mbox_cli
    }
mtk_crtc->cmdq_vblank_cnt = 0;
+ 	wake_up(&mtk_crtc->cb_blocking_queue);
  }
  #endif
@@@ -660,15 -663,15 +662,15 @@@ static void mtk_drm_crtc_atomic_enable(
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
-	ret = mtk_smi_larb_get(comp->larb_dev);
 -	if (ret) {
 -		DRM_ERROR("Failed to get larb: %d\n", ret);
 +	ret = pm_runtime_resume_and_get(comp->dev);
 +	if (ret < 0) {
 +		DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
    	return;
    }
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
    if (ret) {
 -		mtk_smi_larb_put(comp->larb_dev);
 +		pm_runtime_put(comp->dev);
    	return;
    }
@@@ -681,7 -684,7 +683,7 @@@ static void mtk_drm_crtc_atomic_disable
  {
    struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
    struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 -	int i;
 +	int i, ret;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
    if (!mtk_crtc->enabled)
@@@ -699,14 -702,19 +701,21 @@@
    mtk_crtc->pending_planes = true;
mtk_drm_crtc_update_config(mtk_crtc, false);
+ #if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ 	/* Wait for planes to be disabled by cmdq */
+ 	if (mtk_crtc->cmdq_client.chan)
+ 		wait_event_timeout(mtk_crtc->cb_blocking_queue,
+ 				   mtk_crtc->cmdq_vblank_cnt == 0,
+ 				   msecs_to_jiffies(500));
+ #endif
    /* Wait for planes to be disabled */
    drm_crtc_wait_one_vblank(crtc);
drm_crtc_vblank_off(crtc);
    mtk_crtc_ddp_hw_fini(mtk_crtc);
 -	mtk_smi_larb_put(comp->larb_dev);
 +	ret = pm_runtime_put(comp->dev);
 +	if (ret < 0)
 +		DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret);
mtk_crtc->enabled = false;
  }
@@@ -977,6 -985,9 +986,9 @@@ int mtk_drm_crtc_create(struct drm_devi
    			mtk_crtc->cmdq_client.chan = NULL;
    		}
    	}
+ 
+ 		/* for sending blocking cmd in crtc disable */
+ 		init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
    }
  #endif
    return 0;
diff --combined drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b147797177c6,dd029307be7d..838297f9d45d
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@@ -236,6 -236,9 +236,9 @@@ static int mtk_drm_kms_init(struct drm_
    struct device *dma_dev;
    int ret;
+ 	if (drm_firmware_drivers_only())
+ 		return -ENODEV;
+ 
    if (!iommu_present(&platform_bus_type))
    	return -EPROBE_DEFER;
@@@ -645,8 -648,11 +648,8 @@@ err_pm
    pm_runtime_disable(dev);
  err_node:
    of_node_put(private->mutex_node);
 -	for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) {
 +	for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
    	of_node_put(private->comp_node[i]);
 -		if (private->ddp_comp[i].larb_dev)
 -			put_device(private->ddp_comp[i].larb_dev);
 -	}
    return ret;
  }
diff --combined drivers/gpu/drm/nouveau/nouveau_svm.c
index 090b9b47708c,46a5a1016e37..31a5b81ee9fc
--- a/drivers/gpu/drm/nouveau/nouveau_svm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_svm.c
@@@ -35,7 -35,6 +35,7 @@@
  #include <linux/sched/mm.h>
  #include <linux/sort.h>
  #include <linux/hmm.h>
 +#include <linux/memremap.h>
  #include <linux/rmap.h>
struct nouveau_svm {
@@@ -926,8 -925,8 +926,8 @@@ nouveau_pfns_map(struct nouveau_svmm *s
mutex_lock(&svmm->mutex);
- 	ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, sizeof(*args) +
- 				npages * sizeof(args->p.phys[0]), NULL);
+ 	ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args,
+ 				struct_size(args, p.phys, npages), NULL);
mutex_unlock(&svmm->mutex);
  }
diff --combined drivers/gpu/drm/panel/Kconfig
index 9989a316fe88,bb2e47229c68..ddf5f38e8731
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@@ -107,7 -107,6 +107,7 @@@ config DRM_PANEL_ED
    select VIDEOMODE_HELPERS
    select DRM_DP_AUX_BUS
    select DRM_DP_HELPER
 +	select DRM_KMS_HELPER
    help
      DRM panel driver for dumb eDP panels that need at most a regulator and
      a GPIO to be powered up. Optionally a backlight can be attached so
@@@ -294,6 -293,18 +294,18 @@@ config DRM_PANEL_NOVATEK_NT3551
      around the Novatek NT35510 display controller, such as some
      Hydis panels.
+ config DRM_PANEL_NOVATEK_NT35560
+ 	tristate "Novatek NT35560 DSI command mode panel"
+ 	depends on OF
+ 	depends on DRM_MIPI_DSI
+ 	depends on BACKLIGHT_CLASS_DEVICE
+ 	select VIDEOMODE_HELPERS
+ 	help
+ 	  Say Y here if you want to enable the Novatek NT35560 display
+ 	  controller. This panel supports DSI in both command and video
+ 	  mode. This supports several panels such as Sony ACX424AKM and
+ 	  ACX424AKP.
+ 
  config DRM_PANEL_NOVATEK_NT35950
    tristate "Novatek NT35950 DSI panel"
    depends on OF
@@@ -594,17 -605,6 +606,6 @@@ config DRM_PANEL_SITRONIX_ST7789
      Say Y here if you want to enable support for the Sitronix
      ST7789V controller for 240x320 LCD panels
- config DRM_PANEL_SONY_ACX424AKP
- 	tristate "Sony ACX424AKP DSI command mode panel"
- 	depends on OF
- 	depends on DRM_MIPI_DSI
- 	depends on BACKLIGHT_CLASS_DEVICE
- 	select VIDEOMODE_HELPERS
- 	help
- 	  Say Y here if you want to enable the Sony ACX424 display
- 	  panel. This panel supports DSI in both command and video
- 	  mode.
- 
  config DRM_PANEL_SONY_ACX565AKM
    tristate "Sony ACX565AKM panel"
    depends on GPIOLIB && OF && SPI
diff --combined drivers/gpu/drm/panel/panel-simple.c
index b42c1d816e79,c09eb5ad65fc..a34f4198a534
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@@ -2017,7 -2017,7 +2017,7 @@@ static const struct display_timing inno
  static const struct panel_desc innolux_g070y2_l01 = {
    .timings = &innolux_g070y2_l01_timing,
    .num_timings = 1,
 -	.bpc = 6,
 +	.bpc = 8,
    .size = {
    	.width = 152,
    	.height = 91,
@@@ -2526,6 -2526,36 +2526,36 @@@ static const struct panel_desc mitsubis
    .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  };
+ static const struct display_timing multi_inno_mi0700s4t_6_timing = {
+ 	.pixelclock = { 29000000, 33000000, 38000000 },
+ 	.hactive = { 800, 800, 800 },
+ 	.hfront_porch = { 180, 210, 240 },
+ 	.hback_porch = { 16, 16, 16 },
+ 	.hsync_len = { 30, 30, 30 },
+ 	.vactive = { 480, 480, 480 },
+ 	.vfront_porch = { 12, 22, 32 },
+ 	.vback_porch = { 10, 10, 10 },
+ 	.vsync_len = { 13, 13, 13 },
+ 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+ 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
+ 		 DISPLAY_FLAGS_SYNC_POSEDGE,
+ };
+ 
+ static const struct panel_desc multi_inno_mi0700s4t_6 = {
+ 	.timings = &multi_inno_mi0700s4t_6_timing,
+ 	.num_timings = 1,
+ 	.bpc = 8,
+ 	.size = {
+ 		.width = 154,
+ 		.height = 86,
+ 	},
+ 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
+ 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
+ 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
+ 	.connector_type = DRM_MODE_CONNECTOR_DPI,
+ };
+ 
  static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
    .pixelclock = { 68900000, 70000000, 73400000 },
    .hactive = { 1280, 1280, 1280 },
@@@ -3028,6 -3058,7 +3058,7 @@@ static const struct drm_display_mode ro
static const struct panel_desc rocktech_rk101ii01d_ct = {
    .modes = &rocktech_rk101ii01d_ct_mode,
+ 	.bpc = 8,
    .num_modes = 1,
    .size = {
    	.width = 217,
@@@ -3872,6 -3903,9 +3903,9 @@@ static const struct of_device_id platfo
    }, {
    	.compatible = "mitsubishi,aa070mc01-ca1",
    	.data = &mitsubishi_aa070mc01,
+ 	}, {
+ 		.compatible = "multi-inno,mi0700s4t-6",
+ 		.data = &multi_inno_mi0700s4t_6,
    }, {
    	.compatible = "multi-inno,mi1010ait-1cp",
    	.data = &multi_inno_mi1010ait_1cp,
diff --combined drivers/gpu/drm/rockchip/cdn-dp-core.c
index edd6a1fc46cd,4740cc14beb8..d3e6c93739bf
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@@ -16,7 -16,7 +16,7 @@@
  #include <sound/hdmi-codec.h>
#include <drm/drm_atomic_helper.h>
- #include <drm/drm_dp_helper.h>
+ #include <drm/dp/drm_dp_helper.h>
  #include <drm/drm_edid.h>
  #include <drm/drm_of.h>
  #include <drm/drm_probe_helper.h>
@@@ -586,13 -586,6 +586,13 @@@ static bool cdn_dp_check_link_status(st
    return drm_dp_channel_eq_ok(link_status, min(port->lanes, sink_lanes));
  }
+static void cdn_dp_audio_handle_plugged_change(struct cdn_dp_device *dp,
 +					       bool plugged)
 +{
 +	if (dp->codec_dev)
 +		dp->plugged_cb(dp->codec_dev, plugged);
 +}
 +
  static void cdn_dp_encoder_enable(struct drm_encoder *encoder)
  {
    struct cdn_dp_device *dp = encoder_to_dp(encoder);
@@@ -648,9 -641,6 +648,9 @@@
    	DRM_DEV_ERROR(dp->dev, "Failed to valid video %d\n", ret);
    	goto out;
    }
 +
 +	cdn_dp_audio_handle_plugged_change(dp, true);
 +
  out:
    mutex_unlock(&dp->lock);
  }
@@@ -661,8 -651,6 +661,8 @@@ static void cdn_dp_encoder_disable(stru
    int ret;
mutex_lock(&dp->lock);
 +	cdn_dp_audio_handle_plugged_change(dp, false);
 +
    if (dp->active) {
    	ret = cdn_dp_disable(dp);
    	if (ret) {
@@@ -858,27 -846,11 +858,27 @@@ static int cdn_dp_audio_get_eld(struct 
    return 0;
  }
+static int cdn_dp_audio_hook_plugged_cb(struct device *dev, void *data,
 +					hdmi_codec_plugged_cb fn,
 +					struct device *codec_dev)
 +{
 +	struct cdn_dp_device *dp = dev_get_drvdata(dev);
 +
 +	mutex_lock(&dp->lock);
 +	dp->plugged_cb = fn;
 +	dp->codec_dev = codec_dev;
 +	cdn_dp_audio_handle_plugged_change(dp, dp->connected);
 +	mutex_unlock(&dp->lock);
 +
 +	return 0;
 +}
 +
  static const struct hdmi_codec_ops audio_codec_ops = {
    .hw_params = cdn_dp_audio_hw_params,
    .audio_shutdown = cdn_dp_audio_shutdown,
    .mute_stream = cdn_dp_audio_mute_stream,
    .get_eld = cdn_dp_audio_get_eld,
 +	.hook_plugged_cb = cdn_dp_audio_hook_plugged_cb,
    .no_capture_mute = 1,
  };
diff --combined drivers/gpu/drm/rockchip/cdn-dp-core.h
index d808a9de45ed,0d044146f4e9..6d0c5032ef3a
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
@@@ -7,10 -7,9 +7,10 @@@
  #ifndef _CDN_DP_CORE_H
  #define _CDN_DP_CORE_H
- #include <drm/drm_dp_helper.h>
+ #include <drm/dp/drm_dp_helper.h>
  #include <drm/drm_panel.h>
  #include <drm/drm_probe_helper.h>
 +#include <sound/hdmi-codec.h>
#include "rockchip_drm_drv.h"
@@@ -102,8 -101,5 +102,8 @@@ struct cdn_dp_device
u8 dpcd[DP_RECEIVER_CAP_SIZE];
    bool sink_has_audio;
 +
 +	hdmi_codec_plugged_cb plugged_cb;
 +	struct device *codec_dev;
  };
  #endif  /* _CDN_DP_CORE_H */
diff --combined drivers/gpu/drm/tiny/panel-mipi-dbi.c
index 000000000000,7f8c6c51387f..c759ff9c2c87
mode 000000,100644..100644
--- a/drivers/gpu/drm/tiny/panel-mipi-dbi.c
+++ b/drivers/gpu/drm/tiny/panel-mipi-dbi.c
@@@ -1,0 -1,398 +1,396 @@@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+  * DRM driver for MIPI DBI compatible display panels
+  *
+  * Copyright 2022 Noralf Tr��nnes
+  */
+ 
+ #include <linux/backlight.h>
+ #include <linux/delay.h>
+ #include <linux/firmware.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/spi/spi.h>
+ 
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_drv.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_gem_atomic_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_managed.h>
+ #include <drm/drm_mipi_dbi.h>
+ #include <drm/drm_modes.h>
+ #include <drm/drm_modeset_helper.h>
+ 
+ #include <video/mipi_display.h>
+ 
+ static const u8 panel_mipi_dbi_magic[15] = { 'M', 'I', 'P', 'I', ' ', 'D', 'B', 'I',
+ 					     0, 0, 0, 0, 0, 0, 0 };
+ 
+ /*
+  * The display controller configuration is stored in a firmware file.
+  * The Device Tree 'compatible' property value with a '.bin' suffix is passed
+  * to request_firmware() to fetch this file.
+  */
+ struct panel_mipi_dbi_config {
+ 	/* Magic string: panel_mipi_dbi_magic */
+ 	u8 magic[15];
+ 
+ 	/* Config file format version */
+ 	u8 file_format_version;
+ 
+ 	/*
+ 	 * MIPI commands to execute when the display pipeline is enabled.
+ 	 * This is used to configure the display controller.
+ 	 *
+ 	 * The commands are stored in a byte array with the format:
+ 	 *     command, num_parameters, [ parameter, ...], command, ...
+ 	 *
+ 	 * Some commands require a pause before the next command can be received.
+ 	 * Inserting a delay in the command sequence is done by using the NOP command with one
+ 	 * parameter: delay in miliseconds (the No Operation command is part of the MIPI Display
+ 	 * Command Set where it has no parameters).
+ 	 *
+ 	 * Example:
+ 	 *     command 0x11
+ 	 *     sleep 120ms
+ 	 *     command 0xb1 parameters 0x01, 0x2c, 0x2d
+ 	 *     command 0x29
+ 	 *
+ 	 * Byte sequence:
+ 	 *     0x11 0x00
+ 	 *     0x00 0x01 0x78
+ 	 *     0xb1 0x03 0x01 0x2c 0x2d
+ 	 *     0x29 0x00
+ 	 */
+ 	u8 commands[];
+ };
+ 
+ struct panel_mipi_dbi_commands {
+ 	const u8 *buf;
+ 	size_t len;
+ };
+ 
+ static struct panel_mipi_dbi_commands *
+ panel_mipi_dbi_check_commands(struct device *dev, const struct firmware *fw)
+ {
+ 	const struct panel_mipi_dbi_config *config = (struct panel_mipi_dbi_config *)fw->data;
+ 	struct panel_mipi_dbi_commands *commands;
+ 	size_t size = fw->size, commands_len;
+ 	unsigned int i = 0;
+ 
+ 	if (size < sizeof(*config) + 2) { /* At least 1 command */
+ 		dev_err(dev, "config: file size=%zu is too small\n", size);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	if (memcmp(config->magic, panel_mipi_dbi_magic, sizeof(config->magic))) {
+ 		dev_err(dev, "config: Bad magic: %15ph\n", config->magic);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	if (config->file_format_version != 1) {
+ 		dev_err(dev, "config: version=%u is not supported\n", config->file_format_version);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	drm_dev_dbg(dev, DRM_UT_DRIVER, "size=%zu version=%u\n", size, config->file_format_version);
+ 
+ 	commands_len = size - sizeof(*config);
+ 
+ 	while ((i + 1) < commands_len) {
+ 		u8 command = config->commands[i++];
+ 		u8 num_parameters = config->commands[i++];
+ 		const u8 *parameters = &config->commands[i];
+ 
+ 		i += num_parameters;
+ 		if (i > commands_len) {
+ 			dev_err(dev, "config: command=0x%02x num_parameters=%u overflows\n",
+ 				command, num_parameters);
+ 			return ERR_PTR(-EINVAL);
+ 		}
+ 
+ 		if (command == 0x00 && num_parameters == 1)
+ 			drm_dev_dbg(dev, DRM_UT_DRIVER, "sleep %ums\n", parameters[0]);
+ 		else
+ 			drm_dev_dbg(dev, DRM_UT_DRIVER, "command %02x %*ph\n",
+ 				    command, num_parameters, parameters);
+ 	}
+ 
+ 	if (i != commands_len) {
+ 		dev_err(dev, "config: malformed command array\n");
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	commands = devm_kzalloc(dev, sizeof(*commands), GFP_KERNEL);
+ 	if (!commands)
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	commands->len = commands_len;
+ 	commands->buf = devm_kmemdup(dev, config->commands, commands->len, GFP_KERNEL);
+ 	if (!commands->buf)
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	return commands;
+ }
+ 
+ static struct panel_mipi_dbi_commands *panel_mipi_dbi_commands_from_fw(struct device *dev)
+ {
+ 	struct panel_mipi_dbi_commands *commands;
+ 	const struct firmware *fw;
+ 	const char *compatible;
+ 	char fw_name[40];
+ 	int ret;
+ 
+ 	ret = of_property_read_string_index(dev->of_node, "compatible", 0, &compatible);
+ 	if (ret)
+ 		return ERR_PTR(ret);
+ 
+ 	snprintf(fw_name, sizeof(fw_name), "%s.bin", compatible);
+ 	ret = request_firmware(&fw, fw_name, dev);
+ 	if (ret) {
+ 		dev_err(dev, "No config file found for compatible '%s' (error=%d)\n",
+ 			compatible, ret);
+ 
+ 		return ERR_PTR(ret);
+ 	}
+ 
+ 	commands = panel_mipi_dbi_check_commands(dev, fw);
+ 	release_firmware(fw);
+ 
+ 	return commands;
+ }
+ 
+ static void panel_mipi_dbi_commands_execute(struct mipi_dbi *dbi,
+ 					    struct panel_mipi_dbi_commands *commands)
+ {
+ 	unsigned int i = 0;
+ 
+ 	if (!commands)
+ 		return;
+ 
+ 	while (i < commands->len) {
+ 		u8 command = commands->buf[i++];
+ 		u8 num_parameters = commands->buf[i++];
+ 		const u8 *parameters = &commands->buf[i];
+ 
+ 		if (command == 0x00 && num_parameters == 1)
+ 			msleep(parameters[0]);
+ 		else if (num_parameters)
+ 			mipi_dbi_command_stackbuf(dbi, command, parameters, num_parameters);
+ 		else
+ 			mipi_dbi_command(dbi, command);
+ 
+ 		i += num_parameters;
+ 	}
+ }
+ 
+ static void panel_mipi_dbi_enable(struct drm_simple_display_pipe *pipe,
+ 				  struct drm_crtc_state *crtc_state,
+ 				  struct drm_plane_state *plane_state)
+ {
+ 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+ 	struct mipi_dbi *dbi = &dbidev->dbi;
+ 	int ret, idx;
+ 
+ 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
+ 		return;
+ 
+ 	drm_dbg(pipe->crtc.dev, "\n");
+ 
+ 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
+ 	if (ret < 0)
+ 		goto out_exit;
+ 	if (!ret)
+ 		panel_mipi_dbi_commands_execute(dbi, dbidev->driver_private);
+ 
+ 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+ out_exit:
+ 	drm_dev_exit(idx);
+ }
+ 
+ static const struct drm_simple_display_pipe_funcs panel_mipi_dbi_pipe_funcs = {
+ 	.enable = panel_mipi_dbi_enable,
+ 	.disable = mipi_dbi_pipe_disable,
+ 	.update = mipi_dbi_pipe_update,
+ };
+ 
+ DEFINE_DRM_GEM_CMA_FOPS(panel_mipi_dbi_fops);
+ 
+ static const struct drm_driver panel_mipi_dbi_driver = {
+ 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+ 	.fops			= &panel_mipi_dbi_fops,
+ 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
+ 	.debugfs_init		= mipi_dbi_debugfs_init,
+ 	.name			= "panel-mipi-dbi",
+ 	.desc			= "MIPI DBI compatible display panel",
+ 	.date			= "20220103",
+ 	.major			= 1,
+ 	.minor			= 0,
+ };
+ 
+ static int panel_mipi_dbi_get_mode(struct mipi_dbi_dev *dbidev, struct drm_display_mode *mode)
+ {
+ 	struct device *dev = dbidev->drm.dev;
+ 	u16 hback_porch, vback_porch;
+ 	int ret;
+ 
+ 	ret = of_get_drm_panel_display_mode(dev->of_node, mode, NULL);
+ 	if (ret) {
+ 		dev_err(dev, "%pOF: failed to get panel-timing (error=%d)\n", dev->of_node, ret);
+ 		return ret;
+ 	}
+ 
+ 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ 
+ 	hback_porch = mode->htotal - mode->hsync_end;
+ 	vback_porch = mode->vtotal - mode->vsync_end;
+ 
+ 	/*
+ 	 * Make sure width and height are set and that only back porch and
+ 	 * pixelclock are set in the other timing values. Also check that
+ 	 * width and height don't exceed the 16-bit value specified by MIPI DCS.
+ 	 */
+ 	if (!mode->hdisplay || !mode->vdisplay || mode->flags ||
+ 	    mode->hsync_end > mode->hdisplay || (hback_porch + mode->hdisplay) > 0xffff ||
+ 	    mode->vsync_end > mode->vdisplay || (vback_porch + mode->vdisplay) > 0xffff) {
+ 		dev_err(dev, "%pOF: panel-timing out of bounds\n", dev->of_node);
+ 		return -EINVAL;
+ 	}
+ 
+ 	/* The driver doesn't use the pixel clock but it is mandatory so fake one if not set */
+ 	if (!mode->clock)
+ 		mode->clock = mode->htotal * mode->vtotal * 60 / 1000;
+ 
+ 	dbidev->top_offset = vback_porch;
+ 	dbidev->left_offset = hback_porch;
+ 
+ 	return 0;
+ }
+ 
+ static int panel_mipi_dbi_spi_probe(struct spi_device *spi)
+ {
+ 	struct device *dev = &spi->dev;
+ 	struct drm_display_mode mode;
+ 	struct mipi_dbi_dev *dbidev;
+ 	struct drm_device *drm;
+ 	struct mipi_dbi *dbi;
+ 	struct gpio_desc *dc;
+ 	int ret;
+ 
+ 	dbidev = devm_drm_dev_alloc(dev, &panel_mipi_dbi_driver, struct mipi_dbi_dev, drm);
+ 	if (IS_ERR(dbidev))
+ 		return PTR_ERR(dbidev);
+ 
+ 	dbi = &dbidev->dbi;
+ 	drm = &dbidev->drm;
+ 
+ 	ret = panel_mipi_dbi_get_mode(dbidev, &mode);
+ 	if (ret)
+ 		return ret;
+ 
+ 	dbidev->regulator = devm_regulator_get(dev, "power");
+ 	if (IS_ERR(dbidev->regulator))
+ 		return dev_err_probe(dev, PTR_ERR(dbidev->regulator),
+ 				     "Failed to get regulator 'power'\n");
+ 
+ 	dbidev->backlight = devm_of_find_backlight(dev);
+ 	if (IS_ERR(dbidev->backlight))
+ 		return dev_err_probe(dev, PTR_ERR(dbidev->backlight), "Failed to get backlight\n");
+ 
+ 	dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ 	if (IS_ERR(dbi->reset))
+ 		return dev_err_probe(dev, PTR_ERR(dbi->reset), "Failed to get GPIO 'reset'\n");
+ 
+ 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
+ 	if (IS_ERR(dc))
+ 		return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");
+ 
+ 	ret = mipi_dbi_spi_init(spi, dbi, dc);
+ 	if (ret)
+ 		return ret;
+ 
+ 	if (device_property_present(dev, "write-only"))
+ 		dbi->read_commands = NULL;
+ 
+ 	dbidev->driver_private = panel_mipi_dbi_commands_from_fw(dev);
+ 	if (IS_ERR(dbidev->driver_private))
+ 		return PTR_ERR(dbidev->driver_private);
+ 
+ 	ret = mipi_dbi_dev_init(dbidev, &panel_mipi_dbi_pipe_funcs, &mode, 0);
+ 	if (ret)
+ 		return ret;
+ 
+ 	drm_mode_config_reset(drm);
+ 
+ 	ret = drm_dev_register(drm, 0);
+ 	if (ret)
+ 		return ret;
+ 
+ 	spi_set_drvdata(spi, drm);
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
+ 	return 0;
+ }
+ 
 -static int panel_mipi_dbi_spi_remove(struct spi_device *spi)
++static void panel_mipi_dbi_spi_remove(struct spi_device *spi)
+ {
+ 	struct drm_device *drm = spi_get_drvdata(spi);
+ 
+ 	drm_dev_unplug(drm);
+ 	drm_atomic_helper_shutdown(drm);
 -
 -	return 0;
+ }
+ 
+ static void panel_mipi_dbi_spi_shutdown(struct spi_device *spi)
+ {
+ 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
+ }
+ 
+ static int __maybe_unused panel_mipi_dbi_pm_suspend(struct device *dev)
+ {
+ 	return drm_mode_config_helper_suspend(dev_get_drvdata(dev));
+ }
+ 
+ static int __maybe_unused panel_mipi_dbi_pm_resume(struct device *dev)
+ {
+ 	drm_mode_config_helper_resume(dev_get_drvdata(dev));
+ 
+ 	return 0;
+ }
+ 
+ static const struct dev_pm_ops panel_mipi_dbi_pm_ops = {
+ 	SET_SYSTEM_SLEEP_PM_OPS(panel_mipi_dbi_pm_suspend, panel_mipi_dbi_pm_resume)
+ };
+ 
+ static const struct of_device_id panel_mipi_dbi_spi_of_match[] = {
+ 	{ .compatible = "panel-mipi-dbi-spi" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, panel_mipi_dbi_spi_of_match);
+ 
+ static const struct spi_device_id panel_mipi_dbi_spi_id[] = {
+ 	{ "panel-mipi-dbi-spi", 0 },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(spi, panel_mipi_dbi_spi_id);
+ 
+ static struct spi_driver panel_mipi_dbi_spi_driver = {
+ 	.driver = {
+ 		.name = "panel-mipi-dbi-spi",
+ 		.owner = THIS_MODULE,
+ 		.of_match_table = panel_mipi_dbi_spi_of_match,
+ 		.pm = &panel_mipi_dbi_pm_ops,
+ 	},
+ 	.id_table = panel_mipi_dbi_spi_id,
+ 	.probe = panel_mipi_dbi_spi_probe,
+ 	.remove = panel_mipi_dbi_spi_remove,
+ 	.shutdown = panel_mipi_dbi_spi_shutdown,
+ };
+ module_spi_driver(panel_mipi_dbi_spi_driver);
+ 
+ MODULE_DESCRIPTION("MIPI DBI compatible display panel driver");
+ MODULE_AUTHOR("Noralf Tr��nnes");
+ MODULE_LICENSE("GPL");
diff --combined drivers/gpu/drm/tiny/repaper.c
index beeeb170d0b1,5c74e236b16d..37b6bb90e46e
--- a/drivers/gpu/drm/tiny/repaper.c
+++ b/drivers/gpu/drm/tiny/repaper.c
@@@ -508,26 -508,6 +508,6 @@@ static void repaper_get_temperature(str
    epd->factored_stage_time = epd->stage_time * factor10x / 10;
  }
- static void repaper_gray8_to_mono_reversed(u8 *buf, u32 width, u32 height)
- {
- 	u8 *gray8 = buf, *mono = buf;
- 	int y, xb, i;
- 
- 	for (y = 0; y < height; y++)
- 		for (xb = 0; xb < width / 8; xb++) {
- 			u8 byte = 0x00;
- 
- 			for (i = 0; i < 8; i++) {
- 				int x = xb * 8 + i;
- 
- 				byte >>= 1;
- 				if (gray8[y * width + x] >> 7)
- 					byte |= BIT(7);
- 			}
- 			*mono++ = byte;
- 		}
- }
- 
  static int repaper_fb_dirty(struct drm_framebuffer *fb)
  {
    struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
@@@ -560,12 -540,10 +540,10 @@@
    if (ret)
    	goto out_free;
- 	drm_fb_xrgb8888_to_gray8(buf, 0, cma_obj->vaddr, fb, &clip);
+ 	drm_fb_xrgb8888_to_mono_reversed(buf, 0, cma_obj->vaddr, fb, &clip);
drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
- 	repaper_gray8_to_mono_reversed(buf, fb->width, fb->height);
- 
    if (epd->partial) {
    	repaper_frame_data_repeat(epd, buf, epd->current_frame,
    				  REPAPER_NORMAL);
@@@ -1140,12 -1118,14 +1118,12 @@@ static int repaper_probe(struct spi_dev
    return 0;
  }
-static int repaper_remove(struct spi_device *spi)
 +static void repaper_remove(struct spi_device *spi)
  {
    struct drm_device *drm = spi_get_drvdata(spi);
drm_dev_unplug(drm);
    drm_atomic_helper_shutdown(drm);
 -
 -	return 0;
  }
static void repaper_shutdown(struct spi_device *spi)
diff --combined drivers/media/common/videobuf2/videobuf2-dma-contig.c
index 0e3f264122af,ecf065cd4a67..678b359717c4
--- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c
+++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
@@@ -99,7 -99,7 +99,7 @@@ static void *vb2_dc_vaddr(struct vb2_bu
    	return buf->vaddr;
if (buf->db_attach) {
- 		struct dma_buf_map map;
+ 		struct iosys_map map;
if (!dma_buf_vmap(buf->db_attach->dmabuf, &map))
    		buf->vaddr = map.vaddr;
@@@ -132,12 -132,12 +132,12 @@@ static void vb2_dc_prepare(void *buf_pr
    if (!buf->non_coherent_mem)
    	return;
-	/* For both USERPTR and non-coherent MMAP */
 -	dma_sync_sgtable_for_device(buf->dev, sgt, buf->dma_dir);
 -
    /* Non-coherent MMAP only */
    if (buf->vaddr)
    	flush_kernel_vmap_range(buf->vaddr, buf->size);
 +
 +	/* For both USERPTR and non-coherent MMAP */
 +	dma_sync_sgtable_for_device(buf->dev, sgt, buf->dma_dir);
  }
static void vb2_dc_finish(void *buf_priv)
@@@ -152,12 -152,12 +152,12 @@@
    if (!buf->non_coherent_mem)
    	return;
-	/* For both USERPTR and non-coherent MMAP */
 -	dma_sync_sgtable_for_cpu(buf->dev, sgt, buf->dma_dir);
 -
    /* Non-coherent MMAP only */
    if (buf->vaddr)
    	invalidate_kernel_vmap_range(buf->vaddr, buf->size);
 +
 +	/* For both USERPTR and non-coherent MMAP */
 +	dma_sync_sgtable_for_cpu(buf->dev, sgt, buf->dma_dir);
  }
/*********************************************/
@@@ -446,7 -446,7 +446,7 @@@ vb2_dc_dmabuf_ops_end_cpu_access(struc
    return 0;
  }
- static int vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct dma_buf_map *map)
+ static int vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf, struct iosys_map *map)
  {
    struct vb2_dc_buf *buf;
    void *vaddr;
@@@ -456,7 -456,7 +456,7 @@@
    if (!vaddr)
    	return -EINVAL;
- 	dma_buf_map_set_vaddr(map, vaddr);
+ 	iosys_map_set_vaddr(map, vaddr);
return 0;
  }
@@@ -737,7 -737,7 +737,7 @@@ static void vb2_dc_unmap_dmabuf(void *m
  {
    struct vb2_dc_buf *buf = mem_priv;
    struct sg_table *sgt = buf->dma_sgt;
- 	struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buf->vaddr);
+ 	struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr);
if (WARN_ON(!buf->db_attach)) {
    	pr_err("trying to unpin a not attached buffer\n");
diff --combined drivers/video/fbdev/core/fb_defio.c
index d0b0b05e0dff,98b0f23bf5e2..842c66b3e33d
--- a/drivers/video/fbdev/core/fb_defio.c
+++ b/drivers/video/fbdev/core/fb_defio.c
@@@ -59,6 -59,7 +59,7 @@@ static vm_fault_t fb_deferred_io_fault(
    	printk(KERN_ERR "no mapping available\n");
BUG_ON(!page->mapping);
+ 	INIT_LIST_HEAD(&page->lru);
    page->index = vmf->pgoff;
vmf->page = page;
@@@ -95,7 -96,7 +96,7 @@@ static vm_fault_t fb_deferred_io_mkwrit
    struct page *page = vmf->page;
    struct fb_info *info = vmf->vma->vm_private_data;
    struct fb_deferred_io *fbdefio = info->fbdefio;
- 	struct page *cur;
+ 	struct list_head *pos = &fbdefio->pagelist;
/* this is a callback we get when userspace first tries to
    write to the page. we schedule a workqueue. that workqueue
@@@ -122,21 -123,38 +123,38 @@@
     */
    lock_page(page);
- 	/* we loop through the pagelist before adding in order
- 	to keep the pagelist sorted */
- 	list_for_each_entry(cur, &fbdefio->pagelist, lru) {
- 		/* this check is to catch the case where a new
- 		process could start writing to the same page
- 		through a new pte. this new access can cause the
- 		mkwrite even when the original ps's pte is marked
- 		writable */
- 		if (unlikely(cur == page))
- 			goto page_already_added;
- 		else if (cur->index > page->index)
- 			break;
+ 	/*
+ 	 * This check is to catch the case where a new process could start
+ 	 * writing to the same page through a new PTE. This new access
+ 	 * can cause a call to .page_mkwrite even if the original process'
+ 	 * PTE is marked writable.
+ 	 *
+ 	 * TODO: The lru field is owned by the page cache; hence the name.
+ 	 *       We dequeue in fb_deferred_io_work() after flushing the
+ 	 *       page's content into video memory. Instead of lru, fbdefio
+ 	 *       should have it's own field.
+ 	 */
+ 	if (!list_empty(&page->lru))
+ 		goto page_already_added;
+ 
+ 	if (unlikely(fbdefio->sort_pagelist)) {
+ 		/*
+ 		 * We loop through the pagelist before adding in order to
+ 		 * keep the pagelist sorted. This has significant overhead
+ 		 * of O(n^2) with n being the number of written pages. If
+ 		 * possible, drivers should try to work with unsorted page
+ 		 * lists instead.
+ 		 */
+ 		struct page *cur;
+ 
+ 		list_for_each_entry(cur, &fbdefio->pagelist, lru) {
+ 			if (cur->index > page->index)
+ 				break;
+ 		}
+ 		pos = &cur->lru;
    }
- 	list_add_tail(&page->lru, &cur->lru);
+ 	list_add_tail(&page->lru, pos);
page_already_added:
    mutex_unlock(&fbdefio->lock);
@@@ -151,8 -169,15 +169,8 @@@ static const struct vm_operations_struc
    .page_mkwrite	= fb_deferred_io_mkwrite,
  };
-static int fb_deferred_io_set_page_dirty(struct page *page)
 -{
 -	if (!PageDirty(page))
 -		SetPageDirty(page);
 -	return 0;
 -}
 -
  static const struct address_space_operations fb_deferred_io_aops = {
 -	.set_page_dirty = fb_deferred_io_set_page_dirty,
 +	.dirty_folio	= noop_dirty_folio,
  };
int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma)
@@@ -187,7 -212,7 +205,7 @@@ static void fb_deferred_io_work(struct
/* clear the list */
    list_for_each_safe(node, next, &fbdefio->pagelist) {
- 		list_del(node);
+ 		list_del_init(node);
    }
    mutex_unlock(&fbdefio->lock);
  }
diff --combined drivers/video/fbdev/core/fbmem.c
index 8df3ac991e5a,ad9aac06427a..34d6bb1bf82e
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@@ -25,6 -25,7 +25,7 @@@
  #include <linux/init.h>
  #include <linux/linux_logo.h>
  #include <linux/proc_fs.h>
+ #include <linux/platform_device.h>
  #include <linux/seq_file.h>
  #include <linux/console.h>
  #include <linux/kmod.h>
@@@ -396,14 -397,18 +397,14 @@@ static void fb_rotate_logo(struct fb_in
    } else if (rotate == FB_ROTATE_CW) {
    	fb_rotate_logo_cw(image->data, dst, image->width,
    			  image->height);
 -		tmp = image->width;
 -		image->width = image->height;
 -		image->height = tmp;
 +		swap(image->width, image->height);
    	tmp = image->dy;
    	image->dy = image->dx;
    	image->dx = info->var.xres - image->width - tmp;
    } else if (rotate == FB_ROTATE_CCW) {
    	fb_rotate_logo_ccw(image->data, dst, image->width,
    			   image->height);
 -		tmp = image->width;
 -		image->width = image->height;
 -		image->height = tmp;
 +		swap(image->width, image->height);
    	tmp = image->dx;
    	image->dx = image->dy;
    	image->dy = info->var.yres - image->height - tmp;
@@@ -1555,18 -1560,36 +1556,36 @@@ static void do_remove_conflicting_frame
    /* check all firmware fbs and kick off if the base addr overlaps */
    for_each_registered_fb(i) {
    	struct apertures_struct *gen_aper;
+ 		struct device *device;
if (!(registered_fb[i]->flags & FBINFO_MISC_FIRMWARE))
    		continue;
gen_aper = registered_fb[i]->apertures;
+ 		device = registered_fb[i]->device;
    	if (fb_do_apertures_overlap(gen_aper, a) ||
    		(primary && gen_aper && gen_aper->count &&
    		 gen_aper->ranges[0].base == VGA_FB_PHYS)) {
printk(KERN_INFO "fb%d: switching to %s from %s\n",
    		       i, name, registered_fb[i]->fix.id);
- 			do_unregister_framebuffer(registered_fb[i]);
+ 
+ 			/*
+ 			 * If we kick-out a firmware driver, we also want to remove
+ 			 * the underlying platform device, such as simple-framebuffer,
+ 			 * VESA, EFI, etc. A native driver will then be able to
+ 			 * allocate the memory range.
+ 			 *
+ 			 * If it's not a platform device, at least print a warning. A
+ 			 * fix would add code to remove the device from the system.
+ 			 */
+ 			if (dev_is_platform(device)) {
+ 				registered_fb[i]->forced_out = true;
+ 				platform_device_unregister(to_platform_device(device));
+ 			} else {
+ 				pr_warn("fb%d: cannot remove device\n", i);
+ 				do_unregister_framebuffer(registered_fb[i]);
+ 			}
    	}
    }
  }
@@@ -1896,9 -1919,13 +1915,13 @@@ EXPORT_SYMBOL(register_framebuffer)
  void
  unregister_framebuffer(struct fb_info *fb_info)
  {
- 	mutex_lock(&registration_lock);
+ 	bool forced_out = fb_info->forced_out;
+ 
+ 	if (!forced_out)
+ 		mutex_lock(&registration_lock);
    do_unregister_framebuffer(fb_info);
- 	mutex_unlock(&registration_lock);
+ 	if (!forced_out)
+ 		mutex_unlock(&registration_lock);
  }
  EXPORT_SYMBOL(unregister_framebuffer);
diff --combined drivers/video/fbdev/s3c-fb.c
index fe3c8b6935cf,68408c499627..3abbc5737c3b
--- a/drivers/video/fbdev/s3c-fb.c
+++ b/drivers/video/fbdev/s3c-fb.c
@@@ -489,7 -489,7 +489,7 @@@ static int s3c_fb_set_par(struct fb_inf
    struct s3c_fb_win *win = info->par;
    struct s3c_fb *sfb = win->parent;
    void __iomem *regs = sfb->regs;
- 	void __iomem *buf = regs;
+ 	void __iomem *buf;
    int win_no = win->index;
    u32 alpha = 0;
    u32 data;
@@@ -1360,6 -1360,7 +1360,6 @@@ static int s3c_fb_probe(struct platform
    struct device *dev = &pdev->dev;
    struct s3c_fb_platdata *pd;
    struct s3c_fb *sfb;
 -	struct resource *res;
    int win;
    int ret = 0;
    u32 reg;
@@@ -1391,17 -1392,18 +1391,17 @@@
    spin_lock_init(&sfb->slock);
sfb->bus_clk = devm_clk_get(dev, "lcd");
 -	if (IS_ERR(sfb->bus_clk)) {
 -		dev_err(dev, "failed to get bus clock\n");
 -		return PTR_ERR(sfb->bus_clk);
 -	}
 +	if (IS_ERR(sfb->bus_clk))
 +		return dev_err_probe(dev, PTR_ERR(sfb->bus_clk),
 +				     "failed to get bus clock\n");
clk_prepare_enable(sfb->bus_clk);
if (!sfb->variant.has_clksel) {
    	sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
    	if (IS_ERR(sfb->lcd_clk)) {
 -			dev_err(dev, "failed to get lcd clock\n");
 -			ret = PTR_ERR(sfb->lcd_clk);
 +			ret = dev_err_probe(dev, PTR_ERR(sfb->lcd_clk),
 +					    "failed to get lcd clock\n");
    		goto err_bus_clk;
    	}
@@@ -1416,12 -1418,13 +1416,12 @@@
    	goto err_lcd_clk;
    }
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 -	if (!res) {
 -		dev_err(dev, "failed to acquire irq resource\n");
 +	sfb->irq_no = platform_get_irq(pdev, 0);
 +	if (sfb->irq_no < 0) {
    	ret = -ENOENT;
    	goto err_lcd_clk;
    }
 -	sfb->irq_no = res->start;
 +
    ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
    		  0, "s3c_fb", sfb);
    if (ret) {
@@@ -1807,3 -1810,4 +1807,3 @@@ module_platform_driver(s3c_fb_driver)
  MODULE_AUTHOR("Ben Dooks ben@simtec.co.uk");
  MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
  MODULE_LICENSE("GPL");
 -MODULE_ALIAS("platform:s3c-fb");
diff --combined drivers/video/fbdev/udlfb.c
index 90f48b71fd8f,184bb8433b78..b6ec0b8e2b72
--- a/drivers/video/fbdev/udlfb.c
+++ b/drivers/video/fbdev/udlfb.c
@@@ -980,6 -980,7 +980,7 @@@ static int dlfb_ops_open(struct fb_inf
if (fbdefio) {
    		fbdefio->delay = DL_DEFIO_WRITE_DELAY;
+ 			fbdefio->sort_pagelist = true;
    		fbdefio->deferred_io = dlfb_dpy_deferred_io;
    	}
@@@ -1426,7 -1427,7 +1427,7 @@@ static ssize_t metrics_bytes_rendered_s
    			   struct device_attribute *a, char *buf) {
    struct fb_info *fb_info = dev_get_drvdata(fbdev);
    struct dlfb_data *dlfb = fb_info->par;
 -	return snprintf(buf, PAGE_SIZE, "%u\n",
 +	return sysfs_emit(buf, "%u\n",
    		atomic_read(&dlfb->bytes_rendered));
  }
@@@ -1434,7 -1435,7 +1435,7 @@@ static ssize_t metrics_bytes_identical_
    			   struct device_attribute *a, char *buf) {
    struct fb_info *fb_info = dev_get_drvdata(fbdev);
    struct dlfb_data *dlfb = fb_info->par;
 -	return snprintf(buf, PAGE_SIZE, "%u\n",
 +	return sysfs_emit(buf, "%u\n",
    		atomic_read(&dlfb->bytes_identical));
  }
@@@ -1442,7 -1443,7 +1443,7 @@@ static ssize_t metrics_bytes_sent_show(
    			   struct device_attribute *a, char *buf) {
    struct fb_info *fb_info = dev_get_drvdata(fbdev);
    struct dlfb_data *dlfb = fb_info->par;
 -	return snprintf(buf, PAGE_SIZE, "%u\n",
 +	return sysfs_emit(buf, "%u\n",
    		atomic_read(&dlfb->bytes_sent));
  }
@@@ -1450,7 -1451,7 +1451,7 @@@ static ssize_t metrics_cpu_kcycles_used
    			   struct device_attribute *a, char *buf) {
    struct fb_info *fb_info = dev_get_drvdata(fbdev);
    struct dlfb_data *dlfb = fb_info->par;
 -	return snprintf(buf, PAGE_SIZE, "%u\n",
 +	return sysfs_emit(buf, "%u\n",
    		atomic_read(&dlfb->cpu_kcycles_used));
  }
-- 
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